M48Z35Y-70MH1E STMicroelectronics

M48Z35 M48Z35Y 256 Kbit (32 Kbit x 8) ZEROPOWER SRAM Features Integrated, ultra low power SRAM, power-fail control circuit, and battery READ cycle time equals WRITE cycle time 28 Automatic power-fail chip deselect and WRITE 1 protection WRITE protect voltages: PCDIP28 (V = power-fail deselect voltage) PFD battery CAPHAT M48Z35: V = 4.75 to 5.5 V CC 4.5 V V 4.75 V PFD M48Z35Y: 4.5 to 5.5 V SNAPHAT 4.2 V V 4.5 V PFD battery Self-contained battery in the CAPHAT DIP package Packaging includes a 28-lead SOIC and SNAPHAT top (to be ordered separately) Pin and function compatible with JEDEC standard 32 K x 8 SRAMs 28 SOIC package provides direct connection for a 1 SNAPHAT top which contains the battery SOH28 RoHS compliant Lead-free second level interconnect June 2011 Doc ID 2608 Rev 10 1/24 www.st.com 1Contents M48Z35, M48Z35Y Contents 1 Description . 5 2 Operating modes 8 2.1 READ mode 8 2.2 WRITE mode 10 2.3 Data retention mode . 11 2.4 V noise and negative going transients . 13 CC 3 Maximum ratings . 14 4 DC and AC parameters 15 5 Package mechanical data 17 6 Part numbering 21 7 Environmental information . 22 8 Revision history . 23 2/24 Doc ID 2608 Rev 10