STK11C68-M STK11C68-M CMOS nvSRAM High Performance 8K x 8 Nonvolatile Static RAM MIL-STD-883/SMD 5962-92324 DESCRIPTION FEATURES The Simtek STK11C68-M is a fast static RAM (35, 45 35, 45 and 55ns Access Times and 55ns), with a nonvolatile electrically-erasable PROM 17, 20 and 25ns Output Enable Access (EEPROM) element incorporated in each static memory Unlimited Read and Write to SRAM cell. The SRAM can be read and written an unlimited Software STORE Initiation number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to Automatic STORE Timing the EEPROM (STORE), or from the EEPROM to the 100,000 STORE cycles to EEPROM SRAM (RECALL) are initiated through software se- 10 year data retention in EEPROM quences. It combines the high performance and ease Automatic RECALL on Power Up of use of a fast SRAM with nonvolatile data integrity. Software RECALL Initiation The STK11C68-M is pin compatible with industry stan- Unlimited RECALL cycles from EEPROM dard SRAMs and is available in a 28-pin 300 mil Single 5V 10% Operation ceramic DIP or 28-pad LCC package. Commercial and Available in multiple standard packages industrial devices are also available. LOGIC BLOCK DIAGRAM PIN CONFIGURATIONS NC 1 28 V CC 2 27 W A EEPROM ARRAY 12 32 28 27 26 256 x 256 1 A 3 NC 4 26 A NC 7 6 A 4 25 A A 5 25 8 5 A 8 6 A 3 5 24 6 A 5 A 9 A 4 24 A 9 STORE 6 23 A A 11 A A 7 23 A 4 4 3 11 7 22 A G A 8 TOP VIEW 22 G 3 2 A 5 RECALL 8 A 21 A STATIC RAM A 9 21 A 10 1 10 2 9 20 A E 10 20 A A E 1 6 0 ARRAY A 10 19 DQ 7 DQ 11 19 DQ 0 0 7 A 7 DQ 11 18 DQ AA 12 18 6 256 x 256 0 12 DQ DQ 0 1 6 13 14 15 16 17 12 17 DQ DQ A 5 8 1 16 DQ 13 DQ 4 2 A 9 STORE/ 14 15 VSS DQ 3 RECALL A 12 CONTROL 28 - LCC 28 - 300 C-DIP DQ0 COLUMN I/O PIN NAMES DQ1 A - A Address Inputs DQ 0 12 2 COLUMN DECODER W Write Enable DQ3 DQ - DQ Data In/Out 0 7 DQ4 E Chip Enable DQ 5 AA A A A 0112 101 G G Output Enable DQ 6 V Power (+5V) CC DQ7 V Ground SS E W 4-31 INPUT BUFFERS ROW DECODER DQ A 2 7 Vss A 12 DQ NC 3 DQ Vcc 4 DQ W 5STK11C68-M a ABSOLUTE MAXIMUM RATINGS Voltage on typical input relative to V . 0.6V to 7.0V Note a: Stresses greater than those listed underAbsolute Maximum SS Voltage on DQ and G .0.5V to (V +0.5V) Rating may cause permanent damage to the device. This is a stress 0-7 CC Temperature under bias 55C to 125C rating only, and functional operation of the device at conditions above Storage temperature . 65C to 150C those indicated in the operational sections of this specification is not Power dissipation 1W implied. Exposure to absolute maximum rating conditions for extended DC output current .15mA periods may affect reliability. (One output at a time, one second duration) DC CHARACTERISTICS (V = 5.0V 10%) CC SYMBOL PARAMETER MIN MAX UNITS NOTES b I Average V Current 90 mA t = 35ns CC CC AVAV 1 85 mA t = 45ns AVAV 80 mA t = 55ns AVAV d I Average V Current 50 mA E (V 0.2V) CC CC CC 2 during STORE cycle all others V 0.2V or (V 0.2V) IN CC c I Average V Current 27 mA t = 35ns SB CC AVAV 1 (Standby, Cycling TTL Input Levels) 23 mA t = 45ns AVAV 20 mA t = 55ns AVAV E V all others cycling IH c I Average V Current 2 mA E (V 0.2V) SB CC CC 2 (Standby, Stable CMOS Input Levels) all others V 0.2V or (V 0.2V) IN CC I Input Leakage Current (Any Input) 1 AV = max ILK CC V = V to V IN SS CC I Off State Output Leakage Current 5 AV = max OLK CC V = V to V IN SS CC V Input Logic1 Voltage 2.2 V +.5 V All Inputs IH CC V Input Logic0 Voltage V .5 0.8 V All Inputs IL SS V Output Logic1 Voltage 2.4 V I = 4mA OH OUT V Output Logic0 Voltage 0.4 V I = 8mA OL OUT T Operating Temperature 55 125 C A Note b: I is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. CC 1 Note c: Bringing E V will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. IH Note d: I is the average current required for the duration of the store cycle (t ) after the sequence (t ) that initiates the cycle. CC STORE WC 2 AC TEST CONDITIONS Input Pulse Levels . V to 3V SS 5.0V Input Rise and Fall Times 5ns Input and Output Timing Reference Levels 1.5V Output Load . See Figure 1 480 Ohms Output e 30pF CAPACITANCE (T =25C, f=1.0MHz) A INCLUDING 255 Ohms SCOPE SYMBOL PARAMETER MAX UNITS CONDITIONS AND FIXTURE C Input Capacitance 5 pF V = 0 to 3V IN C Output Capacitance 7 pF V = 0 to 3V OUT Note e: These parameters are guaranteed but not tested. Figure 1: AC Output Loading 4-32