PSD813F2A-90J STMicroelectronics

PSD8XXFX Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V Features Flash in-system programmable (ISP) peripheral for 8-bit MCUs Dual bank Flash memories PQFP52 (M) Up to 2 Mbit of primary Flash memory (8 uniform sectors, 32K x8) Up to 256 Kbit secondary Flash memory (4 uniform sectors) Concurrent operation: read from one memory while erasing and writing the other Up to 256 Kbit SRAM 27 reconfigurable I/Oports PLCC52 (J) Enhanced JTAG serial port PLD with macrocells Over 3000 gates of PLD: CPLD and DPLD CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs) DPLD - user defined internal chip select TQFP64 (U) decoding 27 individually configurable I/O port pins Programmable power management They can be used for the following functions: Packages are ECOPACK MCU I/Os PLD I/Os Table 1. Device summary Latched MCU address output Reference Part number Special function I/Os. 16 of the I/O ports may be configured as PSD813F2 open-drain outputs. PSD813F4 In-system programming (ISP) with JTAG PSD813F5 Built-in JTAG compliant serial port allows PSD8XXFX PSD833F2 full-chip in-system programmability Efficient manufacturing allow easy product PSD834F2 testing and programming PSD853F2 Use low cost FlashLINK cable with PC PSD854F2 Page register Internal page register that can be used to expand the microcontroller address space by a factor of 256 May 2009 Doc ID 7833 Rev 7 1/128 www.st.com 1 Contents PSD8XXFX Contents 1 Summary description . 11 2 Pin description 15 3 PSD architectural overview 20 3.1 Memory 20 3.2 Page register 20 3.3 PLDs 20 3.4 I/O ports 21 3.5 MCU bus interface 21 3.6 JTAG port . 21 3.7 In-system programming (ISP) . 21 3.8 Power management unit (PMU) 21 4 Development system . 23 5 PSD register description and address offset 24 6 Detailed operation 26 6.1 Memory blocks . 26 6.2 Description of primary Flash memory and secondary Flash memory . 27 6.3 Memory block select signals 27 6.3.1 Ready/Busy (PC3) . 27 6.3.2 Memory operation . 27 7 Instructions . 30 7.1 Power-up mode 30 7.2 READ 30 7.3 Read memory contents 31 7.4 Read Primary Flash Identifier 31 7.5 Read Memory Sector Protection status 31 7.6 Reading the Erase/Program Status bits 31 7.7 Data Polling flag (DQ7) 32 2/128 Doc ID 7833 Rev 7