PSD4235G2 Flash in-system programmable (ISP) for 16-bit MCUs (5 V supply) Features Dual bank Flash memories 4 Mbit of Primary Flash memory (8 uniform sectors, 32K x 16) 256 Kbit Secondary Flash memory with 4 sectors Concurrent operation: read from one memory while erasing and writing the other 64 Kbit SRAM LQFP80 (U) PLD with macrocells 80-lead, Thin, Quad, Flat Over 3000 gates of PLD: CPLD and DPLD CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs) DPLD - user defined internal chip select decoding Page register 7 L/O ports with 52 I/O pins Internal page register that can be used to 52 individually configurable I/O port pins expand the microcontroller address space that can be used for the following functions: by a factor of 256 MCU I/Os Programmable power management PLD I/Os High endurance Latched MCU address output 100,000 Erase/write c ycles of Flash Special function l/Os memory l/O ports may be configured as open-drain 1,000 Erase/WRITE Cycles of PLD outputs 15 Year Data Retention In-system programming (ISP) with JTAG Single supply voltage Built-in JTAG compliant serial port allows 5V 10% full-chip In-System Programmability Memory speed Efficient manufacturing allow easy product testing and programmingUse low cost 70ns Flash memory and SRAM access FlashLINK cable with PC time Packages are ECOPACK February 2009 Rev 4 1/129 www.st.com 1Contents PSD4235G2 Contents 1 Summary description . 12 1.1 In-system programming (ISP) via JTAG 12 1.1.1 First time programming . 12 1.1.2 Inventory build-up of pre-programmed devices . 12 1.1.3 Expensive sockets . 12 1.2 In-application programming (IAP) . 12 1.2.1 Simultaneous READ and WRITE to Flash memory 13 1.2.2 Complex memory mapping 13 1.2.3 Separate Program and Data space 13 1.3 PSDsoft Express 13 2 Pin description 16 3 PSD architectural overview 21 3.1 Memory 21 3.2 PLDs 21 3.3 I/O ports 21 3.4 MCU bus interface 22 3.5 ISP via JTAG port . 22 3.6 In-System Programming (ISP) . 22 3.7 In-application programming (IAP) . 22 3.8 Page register 22 3.9 Power management unit (PMU) 23 4 Development system . 24 5 PSD register description and address offsets . 26 6 Register bit definition . 28 6.1 Data-In registers - port A, B, C, D, E, F, G 28 6.2 Data-out registers - port A, B, C, D, E, F, G . 28 6.3 Direction registers - ports A, B, C, D, E, F, G 28 6.4 Control registers 28 2/129