STEC01 Datasheet Ground path safety switch with programmable timers Features Input voltage range from 2.2 to 5 V 12 m typ. N-channel FET R DS(on) 7 A continuous current capability PWM control signal from 4 Hz to 5 kHz, with 30% to 100% duty cycle 30 A battery supply current 2 programmable timers: T1, T3 1 fixed timer T2 Input undervoltage lockout VFQFPN 3x3x0.9 16L, 0.5 mm pitch package Applications Electronic cigarettes Timing/reset circuitry Ground path protection circuitry Description The STEC01 is an integrated programmable 12 m power switch managed by the Product status link timer based circuitry. STEC01 The device has 3 timers designed to interrupt the ground path of a power application after a maximum on-time and inhibits the restart of the platform during a cooling Product summary window. The maximum on-time can be set from few seconds to hundreds of seconds, while the cooling window can be programmed to 69, 345 and 1380 seconds. Order code STEC01PUR 3 multi-level input pins, combined with a programmable oscillator and a fixed VFQFPN 3x3x0.9 Package oscillator, are used to set the timing. 16L An input continuous or pulsed signal applied to the PWM pin starts the internal logic and counters. In case of a normal operation, as soon as the activity on the PWM pin stops, the device automatically enters idle mode, waiting for a new valid PWM signal to be applied. If the device detects a fault condition, a reset pulse is generated and the safety MOSFET is turned off and managed according to a predefined state machine. The STEC01 has a continuous current capability up to 7 A through the internal power MOSFET. A higher current can be supported by using an external power transistor driven through GDRV pin. A rising edge on the HW RESET input pin generates a 57 ms pulse on the RESET FAULT pin. This function can be used to notify the connection of an external power source (e.g. USB). DS13063 - Rev 2 - October 2020 www.st.com For further information contact your local STMicroelectronics sales office. STEC01 Block diagram 1 Block diagram Figure 1. Block diagram HW RESET/ VBAT PWM USB conn. Thermal RESET/FAULT shutdown HW Reset PWR T1 LOGIC Safety FET PGND (SF) GDRV T2 TPF T3 OSC1, OSC2, T1P1 Timers T1P2 Decoder T3P AGND DS13063 - Rev 2 page 2/22