STHVDAC-253MF3 STMicroelectronics

STHVDAC-253M Antenna tuning circuit Datasheet production data Description The ST BST capacitance controller STHVDAC-253M is a high voltage digital to analog converter (DAC), specifically designed to control and meet the wide tuning bias voltage requirement of the BST tunable capacitances. It provides 3 independent high voltage outputs, thus having the capability to control 3 different capacitances. It is fully controlled through a RFFE serial interface. BST capacitances are tunable capacitances Lead-free, Flip Chip intended for use in mobile phone application, and (16 bumps) dedicated to RF tunable applications. These tunable capacitances are controlled through a bias voltage ranging from 0 to 25 V. The implementation of BST tunable capacitance in Features mobile phones enables significant improvement in terms of radiated performances, making the Dedicated ASIC to control BST tunable performance almost insensitive to the external capacitances environment. Operation compliant with cellular systems requirements Figure 1. Pin configuration bumps side view Integrated boost converter with 3 3 2 4 1 programmable outputs (from 0 to 25 V) Low power consumption A MIPI RFFE serial interface 1.8 V AVDD IND BOOST GND BOOST DATA Available in WLCSP for stand-alone or SiP module integration B RF tunable passive implementation in mobile VHV GND CLK GND DIG phones to optimize the radiated performances C GND REF GND Application RBIAS VIO Cellular antenna tunable matching network in D multi-band GSM/WCDMA mobile phone OUTC OUTB OUTA SELSID Compatible with open loop antenna tuner applications February 2014 DocID025735 Rev 1 1/27 This is information on a product in full production. www.st.comSTHVDAC-253M Contents 1 Electrical characteristics . 3 2 Functional block diagram . 5 3 Theory of operation 6 3.1 HVDAC output voltages . 6 3.2 Operating modes 8 3.3 Device reset 8 3.4 RFFE serial interface . 9 3.5 RFFE register and write command sequence 9 3.6 RFFE serial interface extended mode 9 3.7 RFFE serial interface brodcast capability 9 3.8 Power-up / down sequence . 10 3.9 Power supply sequencing 10 3.10 Trigger Mode .11 3.10.1 Trigger mode enabled: 11 3.10.2 Trigger mode disabled (default mode): . 11 3.11 Settling time . 12 3.12 Operation with 1 to 3 tunable capacitor 12 4 Registers table . 14 4.1 RFFE interface-register content description . 14 4.2 RFFE interface, command and data frame structure 15 4.3 Changing USID 18 4.4 Serial interface specification . 19 5 Application schematic 21 6 Package information 23 7 Ordering information . 25 8 Revision history . 25 2/27 DocID025735 Rev 1