STNRG328ATR STMicroelectronics

STNRG388A Digital controller for power conversion applications with up to 6 programmable PWM generators, 96 MHz PLL Datasheet - production data 2 Data memory: 1 Kbyte true data E PROM data retention:15 years at 85 C after 100 kcycles at 85 C RAM: 6 Kbytes Clock management Internal 96 MHz PLL Low power oscillator circuit for external crystal resonator or direct clock input Internal, user-trimmable 16 MHz RC and Features low power 153.6 kHz RC oscillators Up to 6 programmable PWM generators Clock security system with clock monitor (SMED - State Machine Event Driven) Basic peripherals 10 ns event detection and reaction System, auxiliary and basic timers Max.1.3 ns PWM resolution IWDG/WWDG watchdog, AWU, ITC Single, coupled and two coupled Reset and supply management operational modes Multiple low power modes (wait, slow, auto- Up to 3 internal/external events per SMED wakeup, Halt) with user definable clock 4 analog comparators gating 4 internal 4-bit references Low consumption power-on and power- Up to 4 external references down reset Less than 50 ns propagation time I/O Continuous comparison cycle Multifunction bidirectional GPIO with highly Configurable hysteresis voltage levels robust design, immune against current injection ADCs (up to 8 channels) Fast digital input DIGIN, with configurable 10-bit precision, with operational amplifier pull-up to extend resolution to 12-bit equivalent Communication interfaces Sequencer functionality UART asynchronous with SW flow control Input impedance: 1 M and bootloader support Configurable gain value: x1 and x4 2 I C master/slave fast-slow speed rate Integrated microcontroller Operating temperature: -40 C up to 105 C. Advanced STM8 core with Harvard architecture and 3-stage pipeline Table 1. Device summary Max. f : 16 MHz CPU Part number Package Memories 2 Flash and E PROM with read while write STNRG388A TSSOP38 (RWW) and error correction code (ECC) Program memory: 32 Kbytes Flash data retention 15 years at 85 C after 10 kcycles at 25 C December 2021 DocID027799 Rev 3 1/122 This is information on a product in full production. www.st.comContents STNRGxxxA Contents 1 Description 11 2 STNRG family features list . 12 3 Introducing SMED 13 Documentation . 13 4 System architecture 14 Block diagram 15 5 Product overview 16 5.1 SMED (state machine event driven): configurable PWM generator . 16 5.1.1 SMED coupling schemes 17 5.1.2 Connection matrix . 18 5.1.3 Architecture and registers . 20 5.1.4 Addressing . 20 5.1.5 Instruction set 20 5.1.6 Single wire interface module (SWIM) 20 5.1.7 Debug module 21 5.2 Basic peripherals . 21 5.2.1 Vectored interrupt controller 21 5.2.2 Timers 21 2 5.2.3 Flash program and data E PROM . 23 5.2.4 Architecture 23 5.2.5 Write protection (WP) . 23 5.2.6 Protection of user boot code (UBC) 23 5.2.7 Read-out protection (ROP) 24 5.3 Clock controller . 24 5.3.1 Internal 16 MHz RC oscillator (HSI) 25 5.3.2 Internal 153.6 kHz RC oscillator (LSI) 25 5.3.3 Internal 96 MHz PLL . 25 5.3.4 External clock input/crystal oscillator (HSE) . 25 5.4 Power management . 26 5.5 Communication interfaces 27 2/122 DocID027799 Rev 3