T810H-6G-TR STMicroelectronics

T810H High temperature 8 A sensitive TRIACs Features A2 Medium current TRIAC Logic level sensitive TRIAC G 150 C max. T turn-off commutation j A1 Clip bounding RoHS (2002/95/EC) compliant packages A2 Applications A2 The T810H is designed for the control of AC actuators in appliances and industrial systems. G G A2 The multi-port drive of the microcontroller can A2 A1 A1 control the multiple loads of such appliances 2 TO-220AB and systems through these sensitive gate D PAK T810H-6T T810H-6G TRIACs. Description Specifically designed to operate at 150 C, the new 8 A T810H TRIACs provide an enhanced performance in terms of power loss and thermal dissipation. This allows the optimization of the heatsink size, leading to space and cost Table 1. Device summary effectiveness when compared to electro- Symbol Value Unit mechanical solutions. I 8A T(RMS) Based on ST logic level technology, they offer an I lower than 10 mA and specified minimal V /V 600 V GT DRM RRM commutation and high noise immunity levels valid I 10 mA GT MAX up to the T max. j May 2009 Doc ID 15714 Rev 1 1/10 www.st.com 10 Characteristics T810H 1 Characteristics Table 2. Absolute maximum ratings Symbol Parameter Value Unit 2 I On-state rms current (full sine wave) D PAK, TO-220AB T = 135 C 8 A T(RMS) c F = 60 Hz t = 16.7 ms 84 Non repetitive surge peak on-state I A TSM current (full cycle, T initial = 25 C) j F = 50 Hz t = 20 ms 80 ItI t Value for fusing t = 10 ms 42 A s p Critical rate of rise of on-state current dI/dt F = 120 Hz T = 150 C 50 A/s j I = 2 x I , t 100 ns G GT r Non repetitive surge peak off-state V /V DRM RRM V /V t = 10 ms T = 25 C V DSM RSM p j voltage + 100 I Peak gate current t = 20 s T = 150 C 4 A GM p j P Average gate power dissipation T = 150 C 1 W G(AV) j T Storage junction temperature range - 40 to + 150 stg C T Operating junction temperature range - 40 to + 150 j Table 3. Electrical characteristics (T = 25 C, unless otherwise specified) j Symbol Test conditions Quadrant Min Max. Unit I I - II - III 1 10 mA GT V = 12 V R = 33 D L V I - II - III 1.0 V GT V V = V , R = 3.3 k I - II - III 0.15 V GD D DRM L (1) I I = 100 mA 25 mA H T I - III 30 I I = 1.2 I mA L G GT II 35 (1) dV/dt V = 67% V gate open, T = 150 C 75 V/s D DRM, j Logic level, 0.1 V/s, T = 150 C 11.4 j (1) (dI/dt)c A/ms Logic level, 15 V/s, T = 150 C 3.0 j 1. For both polarities of A2 referenced to A1. 2/10 Doc ID 15714 Rev 1