UPSD3254A, UPSD3254BV UPSD3253B, UPSD3253BV Flash programmable system devices with 8032 MCU and 256 Kbit SRAM Features Fast 8-bit 8032 MCU 40 MHz at 5.0 V, 24 MHz at 3.3 V Core, 12-clocks per instruction LQFP52 (T) Dual Flash memories with memory LQFP80 (U) 52-lead, thin, 80-lead, thin, quad management quad flat package flat package Place either memory into 8032 program address space or data address space A/D converter Read-while-write operation for in- Four channels, 8-bit resolution, 10 s application programming and EEPROM Communication interfaces emulation USB v1.1, low-speed 1.5 Mbps, Single voltage program and erase 3 endpoints 100,000 minimum erase cycles, 15-year 2 I C master/slave bus controller retention Two UARTs with independent baud rate Clock, reset, and supply management Six I/O ports with up to 46 I/O pins Normal, idle, and power down modes 8032 address/data bus available on Power-on and low voltage reset supervisor TQFP80 package Programmable watchdog timer 5 PWM outputs, 8-bit resolution Programmable logic, general-purpose JTAG in-system programming 16 macrocells Program the entire device in as little as Implements state machines, glue-logic, etc. 10 seconds Timers and interrupts Single supply voltage Three 8032 standard 16-bit timers 4.5 to 5.5 V 10 Interrupt sources with two external 3.0 to 3.6 V interrupt pins ECOPACK packages Table 1. Device summary Max. clock 1st 2nd 8032 Order code SRAM GPIO USB V (V) Pkg. Temp. CC (MHz) Flash Flash bus UPSD3253B-40T6 40 128 KB 32 KB 32 KB 37 No No 4.5-5.5 TQFP52 40C to 85C UPSD3253BV-24T6 24 128 KB 32 KB 32 KB 37 No No 3.0-3.6 TQFP52 40C to 85C UPSD3254BV-24U6 24 256 KB 32 KB 32 KB 46 No Yes 3.0-3.6 TQFP80 40C to 85C UPSD3254A-40T6 40 256 KB 32 KB 32 KB 37 Yes No 4.5-5.5 TQFP52 40C to 85C UPSD3254A-40U6 40 256 KB 32 KB 32 KB 46 Yes Yes 4.5-5.5 TQFP80 40C to 85C January 2009 Rev 5 1/189 www.st.com 1 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Contents UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV Contents 1 UPSD325xx description 9 1.1 52-pin package I/O port 15 2 Architecture overview . 16 2.1 Memory organization 16 2.2 Registers . 16 2.2.1 Accumulator 17 2.2.2 B register 17 2.2.3 Stack pointer . 17 2.2.4 Program counter 18 2.2.5 Program status word . 18 2.2.6 Registers R0~R7 18 2.2.7 Data pointer register . 18 2.3 Program memory . 19 2.4 Data memory 19 2.5 RAM . 19 2.6 XRAM-DDC . 20 2.7 XRAM-PSD . 20 2.8 SFR . 20 2.9 Addressing modes 21 2.9.1 Direct addressing 21 2.9.2 Indirect addressing 22 2.9.3 Register addressing 22 2.9.4 Register-specific addressing . 22 2.9.5 Immediate constants addressing 22 2.9.6 Indexed addressing 22 2.10 Arithmetic instructions . 23 2.11 Logical instructions 24 2.12 Data transfers 25 2.12.1 Internal RAM . 25 2.12.2 External RAM . 28 2.12.3 Lookup tables 28 2.13 Boolean instructions . 29 2/189 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)