TSM9926D Taiwan Semiconductor Dual N-Channel Power MOSFET 20V, 6.0A, 30m FEATURES KEY PERFORMANCE PARAMETERS Advance Trench Process Technology PARAMETER VALUE UNIT High Density Cell Design for Ultra Low On- V 20 V DS resistance V = 4.5V 30 GS R (max) m DS(on) V = 2.5V 40 GS Q 4.86 nC g APPLICATION Specially Designed for Li-on Battery Packs Battery Switch Application SOP-8 Notes: Moisture sensitivity level: level 3. Per J-STD-020 ABSOLUTE MAXIMUM RATINGS (T = 25C unless otherwise noted) A PARAMETER SYMBOL LIMIT UNIT 20 Drain-Source Voltage V V DS 12 Gate-Source Voltage V V GS (Note 1) 6 Continuous Drain Current T = 25C I A C D (Note 2) Pulsed Drain Current I 30 A DM Continuous Source Current (Diode Conduction) I 1.7 A S T = 25C 1.6 A Total Power Dissipation P W DTOT T = 75C 1.1 A Operating Junction and Storage Temperature Range T , T - 55 to +150 C J STG THERMAL PERFORMANCE PARAMETER SYMBOL LIMIT UNIT Junction to Case Thermal Resistance R 40 C/W JC Junction to Ambient Thermal Resistance R 77 C/W JA Notes: R is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined JA at the solder mounting surface of the drain pins. R is guaranteed by design while R is determined by the users board JA CA design. R shown below for single device operation on FR-4 PCB in still air. JA Document Number: DS P0000156 1 Version: B15 Not Recommended TSM9926D Taiwan Semiconductor ELECTRICAL SPECIFICATIONS (T = 25C unless otherwise noted) A PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNIT (Note 3) Static Drain-Source Breakdown Voltage V = 0V, I = 250A BV 20 -- -- V GS D DSS Gate Threshold Voltage V = V , I = 250A V 0.6 -- -- DS GS D GS(TH) V Gate Body Leakage V = 12V, V = 0V I -- -- 100 GS DS GSS nA Zero Gate Voltage Drain Current V = 20V, V = 0V I -- -- 1 A DS GS DSS On-State Drain Current V = 5V, V = 4.5V I 30 -- -- A DS GS D(ON) V = 4.5V, I = 6.0A -- 21 30 GS D Drain-Source On-State Resistance R m DS(ON) V = 2.5V, I = 5.2A -- 30 40 GS D Forward Transconductance V = 10V, I = 6A g -- 30 -- DS D fs S (Note 4) Dynamic Total Gate Charge Q -- 4.86 -- g V = 10V, I = 6A, DS D Gate-Source Charge Q -- 0.92 -- nC gs V = 4.5V GS Gate-Drain Charge Q -- 1.4 -- gd Input Capacitance C -- 562 -- iss pF V = 8V, V = 0V, DS GS Output Capacitance C -- 106 -- oss F = 1.0MHz Reverse Transfer Capacitance C 75 rss (Note 5) Switching Turn-On Delay Time t -- -- 8.1 d(on) V = 10V, DD Turn-On Rise Time t -- 9.95 -- r R = 6, ns GEN Turn-Off Delay Time t -- 21.85 -- d(off) I = 1A, V = 4.5V, D GS Turn-Off Fall Time t -- 5.35 -- f (Note 3) Source-Drain Diode Forward Voltage -- 0.7 1.2 V I = 1.7A, V = 0V V S GS SD Notes: 1. Pulse width limited by the Maximum junction temperature. 2. Surface Mounted on FR4 Board, t 5 sec. 3. Pulse test: PW 300s, duty cycle 2%. 4. For DESIGN AID ONLY, not subject to production testing. 5. Switching time is essentially independent of operating temperature. Document Number: DS P0000156 2 Version: B15 Not Recommended