TC74HC132AF(EL,F) Toshiba

TC74HC132AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC132AP, TC74HC132AF Quad 2-Input Schmitt NAND Gate The TC74HC132A is a high speed CMOS 2-INPUT NAND 2 TC74HC132AP SCHMITT TRIGGER GATE fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Pin configuration and function are the same as the TC74HC00A but the inputs have 25% V hysteresis and with CC its schmitt trigger inputs, the TC74HC132A can be used as a line receiver for slow input signals. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74HC132AF Features High speed: t = 11 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 1 A (max) at Ta = 25C CC High noise immunity: V = 1.1 V at V = 5 V H CC Output drive capability: 10 LSTTL loads Symmetrical output impedance: I = I = 4 mA (min) OH OL Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 to 6 V CC Weight Pin and function compatible with 74LS132 DIP14-P-300-2.54 : 0.96 g (typ.) SOP14-P-300-1.27A : 0.18 g (typ.) Pin Assignment Start of commercial production 1987-11 1 2014-03-01 TC74HC132AP/AF IEC Logic Symbol Truth Table A B Y L L H L H H H L H H H L System Diagram, Waveform Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range V 0.5 to 7 V CC DC input voltage V 0.5 to V + 0.5 V IN CC DC output voltage V 0.5 to V + 0.5 V OUT CC Input diode current I 20 mA IK Output diode current I 20 mA OK DC output current I 25 mA OUT DC V /ground current I 50 mA CC CC Power dissipation P 500 (DIP) (Note 2)/180 (SOP) mW D Storage temperature T 65 to 150 C stg Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = 40 to 65C. From Ta = 65 to 85C a derating factor of 10 mW/C shall be applied until 300 mW. 2 2014-03-01