TC74HC4002AF(F) Toshiba

TC74HC4002AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC4002AP, TC74HC4002AF Dual 4-Input NOR Gate The TC74HC4002A is a high speed CMOS 4-INPUT NOR 2 TC74HC4002AP GATE fabricated with silicon gate C MOS technology. It actives the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including a buffer output, which provide high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features TC74HC4002AF High speed: t = 10 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 1 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Output drive capability: 10 LSTTL loads Symmetrical output impedance: I = I = 4 mA (min) OH OL Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 to 6 V CC Pin and function compatible with 4002B. Weight DIP14-P-300-2.54 : 0.96 g (typ.) SOP14-P-300-1.27A : 0.18 g (typ.) Pin Assignment Start of commercial production 1988-05 1 2014-03-01 TC74HC4002AP/AF IEC Logic Symbol (2) > 1A 1 (3) 1B (1) 1Y (4) 1C (5) 1D (12) 2A (11) 2B (13) 2Y (10) 2C (9) 2D Truth Table A B C D Y H X X X L X H X X L X X H X L X X X H L L L L L H X: Dont care Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range V 0.5 to 7 V CC DC input voltage V 0.5 to V + 0.5 V IN CC DC output voltage V 0.5 to V + 0.5 V OUT CC Input diode current I 20 mA IK Output diode current I 20 mA OK DC output current I 25 mA OUT DC V /ground current I 50 mA CC CC Power dissipation P 500 (DIP) (Note 2)/180 (SOP) mW D Storage temperature T 65 to 150 C stg Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = 40 to 65C. From Ta = 65 to 85C a derating factor of 10 mW/C shall be applied until 300 mW. 2 2014-03-01