TC74HC4017AF(F) Toshiba

TC74HC4017AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC4017AP, TC74HC4017AF Decade Counter/Divider The TC74HC4017A is a high speed CMOS DECADE 2 TC74HC4017AP JOHNSON COUNTER fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaing the CMOS low power dissipation. It contains 5-stage divided-by-10 Johnson counter with 10 decoded output (Q0-Q9) and carry-out bit. This counter is advanced on the positive edge of clock signal when clock enable signal ( CE ) input is held low, or it is advanced on the negative edge of the CE when CK input is held high, and selected one of ten outputs goes high. Holding high the CLR TC74HC4017AF input, this counter is cleared to its zero state without regard to the other input conditions. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: f = 87 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 4 A (max) at Ta = 25C CC Weight High noise immunity: V = V = 28% V (min) NIH NIL CC DlP16-P-300-2.54A : 1.00 g (typ.) Outputs drive capability: 10 LSTTL loads SOP16-P-300-1.27A : 0.18 g (typ.) Symmetrical output impedance: I = I = 4 mA (min) OH OL Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 to 6 V CC Pin and function compatible with 4017B Pin Assignment Start of commercial production 1988-11 1 2014-03-01 TC74HC4017AP/AF IEC Logic symbol Truth Table Inputs Decode Output (H) CK CE CLR X X H Q0 L X L Qn X H L Qn L L Qn + 1 L L Qn H L Qn H L Qn + 1 X: Dont care Carry out H......Q0 to Q4 = H L ......Q5 to Q9 = H System Diagram 2 2014-03-01