TC74HC390AF(F) Toshiba

TC74HC390AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC390AP, TC74HC390AF Dual Decade Counter The TC74HC390A is a high speed CMOS DUAL DECADE 2 TC74HC390AP COUNTER fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It consists of two independent 4-bit counters, each composed of a divide-by-two and a divide-by-five counter. The divide-by-two counter is incremented on the negative going transition of clock A ( CKA ). The divided-by-five counter is incremented on the negative going transition of clock B ( CKB ). The counter can be cascaded to form decade, bi-quinary, or various combinations up to a divide-by-100 counter. When the CLR input is set high, the TC74HC390AF Q outputs are set to low independent of the clock inputs. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: f = 84 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 4 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Output drive capability: 10 LSTTL loads Weight Symmetrical output impedance: I = I = 4 mA (min) OH OL DIP16-P-300-2.54A : 1.00 g (typ.) Balanced propagation delays: t t pLH pHL SOP16-P-300-1.27A : 0.18 g (typ.) Wide operating voltage range: V (opr) = 2 to 6 V CC Pin and function compatible with 74LS390 Pin Assignment Start of commercial production 1986-11 1 2014-03-01 TC74HC390AP/AF IEC Logic Symbol Block Diagram Truth Table Inputs Outputs CKA CKB CLR QA QB QC QD X X H L L L L X L Binary Count Up X L Quinary Count Up X: Dont care 2 2014-03-01