TH58NVG4S0HTAK0 Toshiba

TH58NVG4S0HTAK0 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 16 GBIT (2G 8 BIT) CMOS NAND E PROM DESCRIPTION The TH58NVG4S0HTAK0 is a single 3.3V 16 Gbit (18,253,611,008 bits) NAND Electrically Erasable and 2 Programmable Read-Only Memory (NAND E PROM) organized as (4096 + 256) bytes 64 pages 8192blocks. The device has two 4352-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 4352-byte increments. The Erase operation is implemented in a single block unit (256 Kbytes + 16 Kbytes: 4352 bytes 64 pages). The TH58NVG4S0HTAK0 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES Organization x8 Memory cell array 4352 128K 8 4 Register 4352 8 Page size 4352 bytes Block size (256K + 16K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read Mode control Serial input/output Command control Number of valid blocks Min 8032 blocks Max 8192 blocks Power supply V = 2.7V to 3.6V CC Access time Cell array to register 25 s max Serial Read Cycle 25 ns min (CL=50pF) Program/Erase time Auto Page Program 300 s/page typ. Auto Block Erase 2.5 ms/block typ. Operating current Read (25 ns cycle) 30 mA max. Program (avg.) 30 mA max Erase (avg.) 30 mA max Standby 200 A max Package TSOP I 48-P-1220-0.50 (Weight: 0.56 g typ.) 8 bit ECC for each 512Byte is required. 1 2017-03-24C TH58NVG4S0HTAK0 PIN ASSIGNMENT (TOP VIEW) TH58NVG4S0HTAK0 8 8 NC 1 48 NC NC 2 47 NC NC 3 46 NC NC 4 45 NC NC 5 44 I/O8 RY /BY 2 6 43 I/O7 1 7 42 I/O6 RY /BY 8 41 I/O5 RE CE 1 9 40 NC 2 10 39 NC CE NC 11 38 NC VCC 12 37 VCC V 13 36 V SS SS NC 14 35 NC NC 15 34 NC CLE 16 33 NC ALE 17 32 I/O4 WE 18 31 I/O3 19 30 I/O2 WP NC 20 29 I/O1 NC 21 28 NC NC 22 27 NC NC 23 26 NC NC 24 25 NC PIN NAMES I/O1 to I/O8 I/O port CE 1 Chip enable (Chip A,B) CE 2 Chip enable (Chip C,D) WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect 1 Ready/Busy (Chip A,B) RY/BY RY/BY 2 Ready/Busy (Chip C,D) V Power supply CC V Ground SS NC No Connection 2 2017-03-24C