TH5 8NVG5S0FTAK0 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 32 GBIT (4G 8 BIT) CMOS NAND E PROM DESCRIPTION The TH58NVG5S0F is a single 3.3V 32 Gbit (36,305,895,424 bits) NAND Electrically Erasable and 2 Programmable Read-Only Memory (NAND E PROM) organized as (4096 + 232) bytes 64 pages 16384 blocks. The device has two 4328-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 4328-byte increments. The Erase operation is implemented in a single block unit (256 Kbytes + 14.5 Kbytes: 4328 bytes 64 pages). The TH58NVG5S0F is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES Organization x8 Memory cell array 4328 256K 8 4 Register 4328 8 Page size 4328 bytes Block size (256K + 14.5K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read Mode control Serial input/output Command control Number of valid blocks Min 16064 blocks Max 16384 blocks Power supply V = 2.7V to 3.6V CC Access time Cell array to register 30 s max Serial Read Cycle 25 ns min (CL=100pF) Program/Erase time Auto Page Program 300 s/page typ. Auto Block Erase 3 ms/block typ. Operating current Read (25 ns cycle) 30 mA max. Program (avg.) 30 mA max Erase (avg.) 30 mA max Standby 200 A max Package TSOP I 48-P-1220-0.50C 4bit ECC for each 512Byte is required. 1 2011-07-01C TH5 8NVG5S0FTAK0 PIN ASSIGNMENT (TOP VIEW) TH58NVG5S0FTAK0 8 8 NC 1 48 NC NC 2 47 NC NC 3 46 NC NC 4 45 NC NC 5 44 I/O8 RY /BY 2 6 43 I/O7 1 7 42 I/O6 RY /BY 8 41 I/O5 RE CE 1 9 40 NC 2 10 39 PSL CE NC 11 38 NC V 12 37 V CC CC V 13 36 V SS SS NC 14 35 NC NC 15 34 NC CLE 16 33 NC ALE 17 32 I/O4 WE 18 31 I/O3 19 30 I/O2 WP NC 20 29 I/O1 NC 21 28 NC NC 22 27 NC NC 23 26 NC NC 24 25 NC PINNAMES I/O1 to I/O8 I/O port CE 1 Chip enable (Chip A,B) CE 2 Chip enable (Chip C,D) WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable PSL Power on select Write protect WP RY/BY 1 Ready/Busy (Chip A,B) RY/BY 2 Ready/Busy (Chip C,D) V Power supply CC V Ground SS 2 2011-07-01C