SPICE Device Model SQD30N05-20L Vishay Siliconix N-Channel 55 V (D-S) 175 C MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical N-Channel Vertical DMOS characteristics of the n-channel vertical DMOS. The Macro Model (Subcircuit Model) subcircuit model is extracted and optimized over the - 55 C Level 3 MOS to + 125 C temperature ranges under the pulsed 0 V to 10 V Apply for both Linear and Switching Application gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain Accurate over the - 55 C to + 125 C Temperature Range feedback capacitance network is used to model the gate Model the Gate Charge, Transient, and Diode Reverse charge characteristics while avoiding convergence Recovery Characteristics difficulties of the switched C model. All model parameter gd values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC D C GD R M 1 2 3 DBD Gy Gx + G R G M ETCV C 1 GS S Note This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to the appropriate datasheet of the same number for guaranteed specification limits. Document Number: 67430 www.vishay.com S12-2363-Rev. B, 08-Oct-12 1SPICE Device Model SQD30N05-20L Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J SIMULATED MEASURED PARAMETER SYMBOLTEST CONDITIONS DATA DATA UNIT Static Gate-Source Threshold Voltage V V = V , I = 250 A 1.7 - V GS(th) DS GS D V = 10 V, I = 20 A 0.015 0.016 GS D a Drain-Source On-State Resistance R DS(on) V = 4.5 V, I = 15 A 0.021 0.021 GS D a Forward Transconductance g V = 15 V, I = 20 A 28 34 S fs DS D Body Diode Voltage V I = 80 A 1.2 1.2 V SD S b Dynamic Input Capacitance C 936 938 iss Output Capacitance C 214V = 25 V, V = 0 V, f = 1 MHz203 pF oss DS GS Reverse Transfer Capacitance C 8586 rss Total Gate Charge Q 11 12 g Gate-Source Charge Q 4.1V = 25 V, V = 5 V, I = 35 A4.1 nC gs DS GS D Gate-Drain Charge Q 4.84.8 gd Notes a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. www.vishay.com Document Number: 67430 2 S12-2363-Rev. B, 08-Oct-12