W25M512JW Featuring 1.8V 512M-BIT (2 x 256M-BIT) SERIAL MCP FLASH MEMORY With Multi I/O SPI & Concurrent Operations Publication Release Date: December 24, 2018 - Revision C3 W25M512JW Table of Contents 1. GENERAL DESCRIPTIONS ............................................................................................................. 6 2. FEATURES ....................................................................................................................................... 6 3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 7 3.1 Pad Configuration WSON 8x6-mm ...................................................................................... 7 3.2 Pad Description WSON 8x6-mm .......................................................................................... 7 3.3 Pin Configuration SOIC 300-mil ........................................................................................... 8 3.4 Pin Description SOIC 300-mil ............................................................................................... 8 3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 9 3.6 Ball Description TFBGA 8x6-mm ......................................................................................... 9 4. DEVICE CONFIGURATION & PIN DESCRIPTIONS ..................................................................... 10 4.1 Serial MCP (SpiStack ) Device Configuration ................................................................... 10 4.2 Chip Select (/CS) ................................................................................................................ 10 4.3 Serial Input & Output (DI, DO and IO0, IO1, IO2, IO3) ...................................................... 10 4.4 Serial Clock (CLK) .............................................................................................................. 11 4.5 Reset (/RESET) .................................................................................................................. 11 5. SINGLE DIE (W25Q256JW-IQ) BLOCK DIAGRAM ....................................................................... 12 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 13 6.1 Device Operations .............................................................................................................. 13 6.1.1 Stacked Die Operations ........................................................................................................ 13 6.1.2 Standard SPI Instructions ..................................................................................................... 13 6.1.3 Dual & Quad SPI Instructions ............................................................................................... 14 6.1.4 3-Byte / 4-Byte Address Modes ............................................................................................ 14 6.1.5 Software Reset & Hardware /RESET pin .............................................................................. 14 6.2 Write Protection .................................................................................................................. 15 7. STATUS AND CONFIGURATION REGISTERS ............................................................................ 16 7.1 Status Registers ................................................................................................................. 16 7.1.1 Program/Erase/Write In Progress (BUSY) Status Only .................................................. 16 7.1.2 Write Enable Latch (WEL) Status Only ........................................................................... 16 7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) Volatile/Non-Volatile Writable ........................ 17 7.1.4 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable ........................................ 17 7.1.5 Complement Protect (CMP) Volatile/Non-Volatile Writable ............................................ 17 7.1.6 Status Register Lock (SRL) Volatile/Non-Volatile OTP Writable ..................................... 17 7.1.7 Erase/Program Suspend Status (SUS) Status Only ....................................................... 18 7.1.8 Security Register Lock Bits (LB3, LB2, LB1) Volatile/Non-Volatile OTP Writable ........... 18 7.1.9 Current Address Mode (ADS) Status Only ..................................................................... 18 7.1.10 Power-Up Address Mode (ADP) Non-Volatile Writable ................................................ 18 7.1.11 Write Protect Selection (WPS) Volatile/Non-Volatile Writable ...................................... 18 7.1.12 Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable .......................... 19 7.1.13 Reserved Bits Non Functional ...................................................................................... 19 7.1.14 Single Die W25Q256JW-IQ Status Register Memory Protection (WPS = 0, CMP = 0) ...... 20 7.1.15 Single Die W25Q256JW-IQ Status Register Memory Protection (WPS = 0, CMP = 1) ...... 21 - 1 -