W25N02JWxxIF/IC 1.8V 2G-BIT SERIAL SLC NAND FLASH MEMORY DUAL/QUAD SPI WITH 166MHZ STR & 80MHZ DTR BUFFER READ & CONTINUOUS READ th Release Date: November 18 , 2019 Revision A W25N02JWxxIF/IC Table of Contents 1. GENERAL DESCRIPTIONS ....................................................................................................... 6 2. FEATURES ................................................................................................................................. 6 3. PACKAGE TYPES AND PIN CONFIGURATIONS .................................................................... 7 3.1 Pad Configuration WSON 8x6-mm ................................................................................ 7 3.2 Pad Description WSON 8x6-mm .................................................................................... 7 3.3 Pin Configuration SOIC 300-mil ..................................................................................... 8 3.4 Pin Description SOIC 300-mil ......................................................................................... 8 3.5 Ball Configuration TFBGA 8x6-mm (5x5-1 Ball Array) ................................................... 9 3.6 Ball Description TFBGA 8x6-mm ................................................................................... 9 4. PIN DESCRIPTIONS ................................................................................................................ 10 4.1 Chip Select (/CS) .......................................................................................................... 10 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ............................ 10 4.3 Write Protect (/WP) ....................................................................................................... 10 4.4 HOLD (/HOLD) ............................................................................................................. 10 4.5 Serial Clock (CLK) ........................................................................................................ 10 4.6 Reset (/RESET) ............................................................................................................ 10 5. BLOCK DIAGRAM .................................................................................................................... 11 6. FUNCTIONAL DESCRIPTIONS ............................................................................................... 12 6.1 Device Operation Flow ................................................................................................. 12 6.1.1 Standard SPI Instructions .............................................................................................. 12 6.1.2 Dual SPI Instructions...................................................................................................... 12 6.1.3 Quad SPI Instructions .................................................................................................... 13 6.1.4 DTR Read Instructions ................................................................................................... 13 6.1.5 Hold Function ................................................................................................................. 13 6.1.6 Software Reset & Hardware /RESET pin ....................................................................... 13 6.2 Write Protection ............................................................................................................ 14 6.3 DLP (Data Learning Pattern) ........................................................................................ 15 6.4 Interface States ............................................................................................................ 16 7. PROTECTION, CONFIGURATION AND STATUS REGISTERS ............................................ 17 7.1 Protection Register / Status Register-1 (Volatile Writable, OTP lockable) ................... 17 7.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) Volatile Writable, OTP lockable ........... 17 7.1.2 Write Protection Enable Bit (WP-E) Volatile Writable, OTP lockable .......................... 18 7.1.3 Status Register Protect Bits (SRP1, SRP0) Volatile Writable, OTP lockable .............. 18 7.2 Configuration Register / Status Register-2 (Volatile Writable ...................................... 19 7.2.1 One Time Program Lock Bit (OTP-L) OTP lockable.................................................... 19 7.2.2 Enter OTP Access Mode Bit (OTP-E) Volatile Writable .............................................. 19 7.2.3 Status Register-1 Lock Bit (SR1-L) OTP lockable ....................................................... 19 7.2.4 ECC Enable Bit (ECC-E) Volatile Writable .................................................................. 20 7.2.5 Buffer Read / Continuous Read Mode Bit (BUF) Volatile Writable .............................. 20 7.2.6 Quad Enable (QE) Volatile Writable ............................................................................ 20 7.3 Status Register-3 (Status only) .................................................................................... 21 7.3.1 Look-Up Table Full (LUT-F) Status Only ..................................................................... 21 7.3.2 Cumulative ECC Status (ECC-1, ECC-0) Status Only ................................................ 21 7.3.3 Program Failure (P-FAIL) Status Only ........................................................................ 22 th Release Date: November 18 , 2019 - 1 - Revision A