W25N02KVxxIR/U 3V 2G-BIT SLC QSPINAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & SEQUENTIAL READ Publication Release Date: March 24, 2021 Revision F W25N02KVxxIR/U Table of Contents 1. GENERAL DESCRIPTIONS ............................................................................................................. 6 2. FEATURES ....................................................................................................................................... 6 3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 7 3.1 Pad Configuration WSON 8x6-mm ...................................................................................... 7 3.2 Pad Description WSON 8x6-mm .......................................................................................... 7 3.3 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8 3.4 Ball Description TFBGA 8x6-mm ......................................................................................... 8 4. PIN CONFIGURATION SOIC 300-MIL............................................................................................. 9 5. PIN DESCRIPTION SOIC 300-MIL .................................................................................................. 9 6. PIN DESCRIPTIONS ...................................................................................................................... 10 6.1 Chip Select (/CS) ................................................................................................................ 10 6.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................. 10 6.3 Write Protect (/WP) ............................................................................................................. 10 6.4 HOLD (/HOLD) ................................................................................................................... 10 6.5 Serial Clock (CLK) .............................................................................................................. 10 7. BLOCK DIAGRAM .......................................................................................................................... 11 8. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 12 8.1 Device Operation Flow ....................................................................................................... 12 8.1.1 Standard SPI Instructions ..................................................................................................... 12 8.1.2 Dual SPI Instructions ............................................................................................................ 12 8.1.3 Quad SPI Instructions ........................................................................................................... 13 8.1.4 Hold Function ........................................................................................................................ 13 8.2 Write Protection .................................................................................................................. 14 9. PROTECTION, CONFIGURATION AND STATUS REGISTERS .................................................. 15 9.1 Protection Register / Status Register-1 (Volatile Writable, OTP lockable) ......................... 15 9.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) Volatile Writable, OTP lockable .................. 15 9.1.2 Write Protection Enable Bit (WP-E) Volatile Writable, OTP lockable ................................. 16 9.1.3 Status Register Protect Bits (SRP1, SRP0) Volatile Writable, OTP lockable ..................... 16 9.2 Configuration Register / Status Register-2 (Volatile Writable) ........................................... 17 9.2.1 One Time Program Lock Bit (OTP-L) OTP lockable .......................................................... 17 9.2.2 Enter OTP Access Mode Bit (OTP-E) Volatile Writable ..................................................... 17 9.2.3 Status Register-1 Lock Bit (SR1-L) OTP lockable ............................................................. 17 9.2.4 ECC Enable Bit (ECC-E) Volatile Writable ......................................................................... 18 9.2.5 Output Driver Strength (ODS-1, ODS-0) Volatile Writable ................................................. 20 9.2.6 Hold Disable (H-DIS) Volatile Writable............................................................................... 20 9.2.7 Buffer Read / Sequential Read Mode Bit (BUF) Volatile Writable ...................................... 20 9.3 Status Register-3 (Status Only) .......................................................................................... 21 9.3.1 Cumulative ECC Status (ECC-1, ECC-0) Status Only ....................................................... 21 9.3.2 Program/Erase Failure (P-FAIL, E-FAIL) Status Only ........................................................ 22 9.3.3 Write Enable Latch (WEL) Status Only .............................................................................. 22 9.3.4 Erase/Program In Progress (BUSY) Status Only ............................................................... 22 9.4 Extended internal ECC feature registers ............................................................................ 23 Publication Release Date: March 24, 2021 - 1 - Revision F