W25Q40CL 2.5/3/3.3V 4 M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS, DUAL AND QUAD SPI Publication Release Date: July 28, 2017 - 1 - Revision E W25Q40CL Table of Contents 1. GENERAL DESCRIPTION ......................................................................................................... 5 2. FEATURES ................................................................................................................................. 5 3. PIN CONFIGURATION SOIC 150-MIL, VSOP 150-MIL, TSSOP 173-MIL ................................ 6 4. PAD CONFIGURATION USON 2X3-MM ................................................................................... 6 5. PIN DESCRIPTION SOIC 150-MIL ............................................................................................ 6 5.1 Package Types ............................................................................................................... 7 5.2 Chip Select (/CS) ............................................................................................................ 7 5.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ............................... 7 5.4 Write Protect (/WP) ......................................................................................................... 7 5.5 HOLD (/HOLD)................................................................................................................ 7 5.6 Serial Clock (CLK) .......................................................................................................... 7 6. BLOCK DIAGRAM ...................................................................................................................... 8 7. FUNCTIONAL DESCRIPTION.................................................................................................... 9 7.1 SPI OPERATIONS ......................................................................................................... 9 7.1.1 Standard SPI Instructions ................................................................................................. 9 7.1.2 Dual SPI Instructions ........................................................................................................ 9 7.1.3 Quad SPI Instructions....................................................................................................... 9 7.1.4 Hold Function ................................................................................................................... 9 7.2 WRITE PROTECTION .................................................................................................. 10 7.2.1 Write Protect Features .................................................................................................... 10 8. CONTROL AND STATUS REGISTERS ................................................................................... 11 8.1 STATUS REGISTER .................................................................................................... 11 8.1.1 BUSY .............................................................................................................................. 11 8.1.2 Write Enable Latch (WEL) .............................................................................................. 11 8.1.3 Block Protect Bits (BP2, BP1, BP0) ................................................................................ 11 8.1.4 Top/Bottom Block Protect (TB) ....................................................................................... 11 8.1.5 Sector/Block Protect (SEC) ............................................................................................ 11 8.1.6 Complement Protect (CMP) ........................................................................................... 11 8.1.7 Status Register Protect (SRP1, SRP0)........................................................................... 12 8.1.8 Erase/Program Suspend Status (SUS) .......................................................................... 12 8.1.9 Security Register Lock Bits (LB3, LB2, LB1, LB0) .......................................................... 12 8.1.10 Quad Enable (QE) ........................................................................................................ 13 8.1.11 Status Register Memory Protection (CMP = 0) ............................................................. 14 8.1.12 Status Register Memory Protection (CMP = 1) ............................................................. 15 9. INSTRUCTIONS ....................................................................................................................... 16 9.1.1 Manufacturer and Device Identification .......................................................................... 16 9.1.2 Instruction Set Table 1 (Erase, Program Instructions) .................................................... 17 9.1.3 Instruction Set Table 2 (Read Instructions) .................................................................... 18 9.1.4 Instruction Set Table 3 (ID, Security Instructions) .......................................................... 19 9.1.5 Write Enable (06h).......................................................................................................... 20 9.1.6 Write Enable for Volatile Status Register (50h) .............................................................. 20 9.1.7 Write Disable (04h) ......................................................................................................... 21 9.1.8 Read Status Register-1 (05h) and Read Status Register-2 (35h) .................................. 21 Publication Release Date: July 28, 2017 - 2 - Revision E