W25R256JV 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & RPMC Publication Release Date: June 16, 2020 Preliminary - Revision D W25R256JV Table of Contents 1. GENERAL DESCRIPTIONS ............................................................................................................. 5 2. FEATURES ....................................................................................................................................... 5 3. PACKAGE TYPES AND PIN CONFIGURATIONS ........................................................................... 6 3.1 Pad Configuration WSON 8x6-mm ...................................................................................... 6 3.2 Pad Description WSON 8x6-mm .......................................................................................... 6 3.3 Pin Configuration SOIC 300-mil ........................................................................................... 7 3.4 Pin Description SOIC 300-mil ............................................................................................... 7 4. PIN DESCRIPTIONS ........................................................................................................................ 8 4.1 Chip Select (/CS) .................................................................................................................. 8 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 8 4.3 Serial Clock (CLK) ................................................................................................................ 8 5. BLOCK DIAGRAM ............................................................................................................................ 9 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 10 6.1 SPI Operations ................................................................................................................... 10 6.1.1 Standard SPI Instructions ..................................................................................................... 10 6.1.2 Dual SPI Instructions ............................................................................................................ 10 6.1.3 Quad SPI Instructions ........................................................................................................... 11 6.1.4 3-Byte / 4-Byte Address Modes ............................................................................................ 11 6.1.5 Software Reset ..................................................................................................................... 11 6.2 RPMC OPERATIONS ........................................................................................................ 12 6.2.1 RPMC Initialization ............................................................................................................... 12 6.2.2 RPMC Operation Flow .......................................................................................................... 13 6.2.3 Operations Allowed / Disallowed During RPMC Operation .................................................. 14 6.2.4 RPMC Status Register Definition .......................................................................................... 15 6.3 Write Protection .................................................................................................................. 16 7. STATUS AND CONFIGURATION REGISTERS ............................................................................ 17 7.1 Status Registers ................................................................................................................. 17 7.1.1 Erase/Write In Progress (BUSY) Status Only ................................................................ 17 7.1.2 Write Enable Latch (WEL) Status Only .......................................................................... 17 7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) Volatile/Non-Volatile Writable ....................... 18 7.1.4 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable ....................................... 18 7.1.5 Complement Protect (CMP) Volatile/Non-Volatile Writable ............................................ 18 7.1.6 Status Register Protect (SRP1, SRP0) Volatile/Non-Volatile Writable ........................... 18 7.1.7 Erase/Program Suspend Status (SUS) Status Only....................................................... 19 7.1.8 Security Register Lock Bits (LB3, LB2, LB1) Volatile/Non-Volatile OTP Writable .......... 19 7.1.9 Quad Enable (QE) Volatile/Non-Volatile Writable .......................................................... 19 7.1.10 Current Address Mode (ADS) Status Only ................................................................... 20 - 1 -