X-On Electronics has gained recognition as a prominent supplier of W9712G6KB25I TR DRAM across the USA, India, Europe, Australia, and various other global locations. W9712G6KB25I TR DRAM are a product manufactured by Winbond. We provide cost-effective solutions for DRAM, ensuring timely deliveries around the world.

W9712G6KB25I TR Winbond

W9712G6KB25I TR electronic component of Winbond
W9712G6KB25I TR Winbond
W9712G6KB25I TR DRAM
W9712G6KB25I TR  Semiconductors

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Part No. W9712G6KB25I TR
Manufacturer: Winbond
Category: DRAM
Description: DRAM 128Mb DDR2-800, x16 T&R
Datasheet: W9712G6KB25I TR Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
1: USD 2.55 ea
Line Total: USD 2.55 
Availability - 2400
Ship by Mon. 27 Jan to Wed. 29 Jan
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
2400
Ship by Mon. 27 Jan to Wed. 29 Jan
MOQ : 1
Multiples : 1
1 : USD 2.55
10 : USD 2.1505
100 : USD 1.848
500 : USD 1.793
1000 : USD 1.683
2500 : USD 1.595
25000 : USD 1.584

   
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We are delighted to provide the W9712G6KB25I TR from our DRAM category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the W9712G6KB25I TR and other electronic components in the DRAM category and beyond.

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W9712G6KB 2M 4 BANKS 16 BIT DDR2 SDRAM Table of Contents- 1. GENERAL DESCRIPTION ................................................................................................................... 4 2. FEATURES ........................................................................................................................................... 4 3. ORDER INFORMATION ....................................................................................................................... 4 4. KEY PARAMETERS ............................................................................................................................. 5 5. BALL CONFIGURATION ...................................................................................................................... 6 6. BALL DESCRIPTION ............................................................................................................................ 7 7. BLOCK DIAGRAM ................................................................................................................................ 8 8. FUNCTIONAL DESCRIPTION .............................................................................................................. 9 8.1 Power-up and Initialization Sequence ................................................................................................... 9 8.2 Mode Register and Extended Mode Registers Operation ................................................................... 10 8.2.1 Mode Register Set Command (MRS)............................................................................... 10 8.2.2 Extend Mode Register Set Commands (EMRS) .............................................................. 11 8.2.2.1 Extend Mode Register Set Command (1), EMR (1) ................................................ 11 8.2.2.2 DLL Enable/Disable ................................................................................................ 12 8.2.2.3 Extend Mode Register Set Command (2), EMR (2) ................................................ 13 8.2.2.4 Extend Mode Register Set Command (3), EMR (3) ................................................ 14 8.2.3 Off-Chip Driver (OCD) Impedance Adjustment ................................................................ 15 8.2.3.1 Extended Mode Register for OCD Impedance Adjustment .................................... 16 8.2.3.2 OCD Impedance Adjust .......................................................................................... 16 8.2.3.3 Drive Mode ............................................................................................................. 17 8.2.4 On-Die Termination (ODT) ............................................................................................... 18 8.2.5 ODT related timings ......................................................................................................... 18 8.2.5.1 MRS command to ODT update delay ..................................................................... 18 8.3 Command Function ............................................................................................................................. 20 8.3.1 Bank Activate Command .................................................................................................. 20 8.3.2 Read Command ............................................................................................................... 20 8.3.3 Write Command ............................................................................................................... 21 8.3.4 Burst Read with Auto-precharge Command ..................................................................... 21 8.3.5 Burst Write with Auto-precharge Command ..................................................................... 21 8.3.6 Precharge All Command .................................................................................................. 21 8.3.7 Self Refresh Entry Command .......................................................................................... 21 8.3.8 Self Refresh Exit Command ............................................................................................. 22 8.3.9 Refresh Command ........................................................................................................... 22 8.3.10 No-Operation Command .................................................................................................. 23 8.3.11 Device Deselect Command .............................................................................................. 23 8.4 Read and Write access modes ........................................................................................................... 23 8.4.1 Posted CAS ................................................................................................................... 23 CAS 8.4.1.1 Examples of posted operation ..................................................................... 23 8.4.2 Burst mode operation ....................................................................................................... 24 8.4.3 Burst read mode operation ............................................................................................... 25 8.4.4 Burst write mode operation .............................................................................................. 25 8.4.5 Write data mask ............................................................................................................... 26 8.5 Burst Interrupt ..................................................................................................................................... 26 8.6 Precharge operation ............................................................................................................................ 27 Publication Release Date: Apr. 13, 2018 Revision: A06 - 1 - W9712G6KB 8.6.1 Burst read operation followed by precharge ..................................................................... 27 8.6.2 Burst write operation followed by precharge .................................................................... 27 8.7 Auto-precharge operation ................................................................................................................... 27 8.7.1 Burst read with Auto-precharge ....................................................................................... 28 8.7.2 Burst write with Auto-precharge ....................................................................................... 28 8.8 Refresh Operation ............................................................................................................................... 29 8.9 Power Down Mode .............................................................................................................................. 29 8.9.1 Power Down Entry ........................................................................................................... 30 8.9.2 Power Down Exit .............................................................................................................. 30 8.10 Input clock frequency change during precharge power down ............................................................. 30 9. OPERATION MODE ........................................................................................................................... 31 9.1 Command Truth Table ........................................................................................................................ 31 9.2 Clock Enable (CKE) Truth Table for Synchronous Transitions ........................................................... 32 9.3 Data Mask (DM) Truth Table ............................................................................................................... 32 9.4 Function Truth Table ........................................................................................................................... 33 9.5 Simplified Stated Diagram ................................................................................................................... 36 10. ELECTRICAL CHARACTERISTICS ................................................................................................... 37 10.1 Absolute Maximum Ratings ................................................................................................................ 37 10.2 Operating Temperature Condition ....................................................................................................... 37 10.3 Recommended DC Operating Conditions ........................................................................................... 37 10.4 ODT DC Electrical Characteristics ...................................................................................................... 38 10.5 Input DC Logic Level ........................................................................................................................... 38 10.6 Input AC Logic Level ........................................................................................................................... 38 10.7 Capacitance ........................................................................................................................................ 39 10.8 Leakage and Output Buffer Characteristics ........................................................................................ 39 10.9 DC Characteristics .............................................................................................................................. 40 10.10 IDD Measurement Test Parameters .......................................................................................... 42 10.11 AC Characteristics ..................................................................................................................... 43 10.12 AC Input Test Conditions ........................................................................................................... 64 10.13 Differential Input/Output AC Logic Levels .................................................................................. 64 10.14 AC Overshoot / Undershoot Specification ................................................................................. 65 10.14.1 AC Overshoot / Undershoot Specification for Address and Control Pins: ........................ 65 10.14.2 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins: .......... 65 11. TIMING WAVEFORMS ....................................................................................................................... 66 11.1 Command Input Timing ....................................................................................................................... 66 11.2 ODT Timing for Active/Standby Mode ................................................................................................. 67 11.3 ODT Timing for Power Down Mode .................................................................................................... 67 11.4 ODT Timing mode switch at entering power down mode .................................................................... 68 11.5 ODT Timing mode switch at exiting power down mode ...................................................................... 69 11.6 Data output (read) timing .................................................................................................................... 70 11.7 Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................ 70 11.8 Data input (write) timing ...................................................................................................................... 71 11.9 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4) .................................................................... 71 11.10 Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) ...................................... 72 11.11 Seamless burst write operation: RL = 5 ( WL = 4, BL = 4) ......................................................... 72 11.12 Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) ............................................................. 73 11.13 Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) .................................................. 73 11.14 Write operation with Data Mask: WL=3, AL=0, BL=4) ............................................................... 74 11.15 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP 2clks) ............ 75 11.16 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP 2clks) ............ 75 Publication Release Date: Apr. 13, 2018 Revision: A06 - 2 -

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:
WINBOND ELECTRONICS
WINBOND ELECTRONICS CORP AMERICA
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