Virtex-7 FPGA VC7222 GTH and GTZ Transceiver Characterization Board User Guide UG965 (v1.4) February 11, 2015DISCLAIMER The information disclosed to you hereunder (the Materials) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made availableAS I and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinxs limited warranty, please refer to Xilinxs Terms of Sale which can be viewed at www.xilinx.com/legal.htm tos IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinxs Terms of Sale which can be viewed at www.xilinx.com/legal.htm tos. Copyright 20132015 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 01/25/2013 1.0 Initial Xilinx release. 01/30/2013 1.0.1 Corrected callout links located throughout the body text back to Table 1-1, page 7. Added answer record link in References, page 61. 07/23/2013 1.1 In Table 1-4, changed nominal voltage to 1.075 V. In Figure 1-3, changed MGTZAVCC and MGTZVCCL voltages to 1.075V. Added a footnote about critical signals to Table 1-20 and Table 1-21. In Appendix C, replaced user constraints file (UCF) with Xilinx Design Constraints (XDC) information. Updated links. 09/20/2013 1.1.1 Updated the Virtex-7 FPGA VC7222 IBERT Getting Started Guide (Vivado Design Suite) (UG971) link in Appendix D, Additional Resources. 12/18/2013 1.2 Revised Table 1-7 through Table 1-12, Table 1-18, and Table 1-19. Rearranged rows in Table 1-21. Updated references in Appendix D, Additional Resources. Updated the Declaration of Conformity link in Appendix E, Regulatory and Compliance Information. 08/21/2014 1.3 The number of 7 series GTH power modules from third-party vendors supplied with the VC7222 board changed from four to two. Appendix C was renamed Master Constraints File Listing. Intersil and Lineage vendors were removed from References, page 61. 02/11/2015 1.4 Two power modules are provided with the VC7222 boardTexas Instruments PMP6577 and Bellnix BPE-37 (for 7 Series GTH Transceiver Power Module, page 13 and 7 Series GTZ Transceiver Power Module, page 15. Updated VC7222 Board XDC Listing, page 47. VC7222 Transceiver Characterization Board www.xilinx.com UG965 (v1.4) February 11, 2015