XA Zynq-7000 SoC Data Sheet: Overview DS188 (v1.3.2) July 2, 2018 Product Specification XA Zynq-7000 SoC First Generation Architecture The XA Zynq-7000 Automotive family is based on the Xilinx SoC architecture. These products integrate a feature-rich dual-core ARM Cortex-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. This highly integrated, flexible, and power-optimized solution is ideal for high computationally intensive and performance demanding applications. The automotive family focuses on automotive applications and consists of the Z-7010, Z-7020, and Z-7030 devices. Processing System (PS) Dual-Core ARM Cortex-A9 Based Caches Application Processor Unit (APU) 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU) 2.5 DMIPS/MHz per CPU 512 KB 8-way set-associative Level 2 cache CPU frequency: Up to 667 MHz (shared between the CPUs) Coherent multiprocessor support Byte-parity support ARMv7-A architecture TrustZone security On-Chip Memory Thumb-2 instruction set On-chip boot ROM Jazelle RCT execution Environment Architecture 256 KB on-chip RAM (OCM) NEON media-processing engine Byte-parity support Single and double precision Vector Floating Point Unit (VFPU) External Memory Interfaces CoreSight technology and Program Trace Multiprotocol dynamic memory controller Macrocell (PTM) 16-bit or 32-bit interfaces to DDR3L, DDR3, Timer and Interrupts DDR2, or LPDDR2 memories Three watchdog timers ECC support in 16-bit mode One global timer 1 GB of address space using single rank of 8-, Two triple-timer counters 16-, or 32-bit-wide memories Static memory interfaces Copyright 20122018 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS188 (v1.3.2) July 2, 2018 www.xilinx.com Product Specification 1XA Zynq-7000 SoC Data Sheet: Overview 8-bit SRAM data bus with up to 64 MB GPIO with four 32-bit banks, of which up to 54 support bits can be used with the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits (up Parallel NOR flash support to two banks of 32b) connected to the ONFI1.0 NAND flash support (1-bit ECC) programmable logic (PL) 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or Up to 54 flexible multiplexed I/O (MIO) for two quad-SPI (8-bit) serial NOR flash peripheral pin assignments 8-Channel DMA Controller Interconnect Memory-to-memory, memory-to-peripheral, High-bandwidth connectivity within PS and peripheral-to-memory, and scatter-gather between PS and PL transaction support ARM AMBA AXI based QoS support on critical masters for latency and I/O Peripherals and Interfaces bandwidth control Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support Scatter-gather DMA capability Recognition of 1588 rev. 2 PTP frames GMII and RGMII interfaces Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints USB 2.0 compliant device IP core On-the-go, high-speed, full-speed, and low-speed modes support Intel EHCI compliant USB host 8-bit ULPI external PHY interface Two full CAN 2.0B compliant CAN bus interfaces CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard compliant External PHY interface Two SD/SDIO 2.0/MMC3.31 compliant controllers Two full-duplex SPI ports with three peripheral chip selects Two high-speed UARTs (up to 1 Mb/s) Two master and slave I2C interfaces DS188 (v1.3.2) July 2, 2018 www.xilinx.com Product Specification 2