CUSTOMER PROCUREMENTSPECIFICATION 216COl/CO2 CPU CENTRALPROCESSINGUNIT FEATURES Memory Memory Speed H Extendable Register Files Address Extension Part (MHz) Zi 6COl 8 Mbytes 48 Mbytes 10 Z16CO2 64 Kbytes 384 Kbytes 10 1 Nine Basic Instruction Types n Eight User-Selectable Addressing Modes n 40/48-Pin PDIP and 44-Pin PLCC Packages n Seven Data Types n +4.5 I V,, I +5.5-Volt Operating Range H Supports Three Interrupt Types and Four Traps n Low-Power CMOS n RISC-Like Load/Store Architecture n 0C to +70C Temperature Range GENERAL DESCRIPTION The Z16COl/CO2 CPU are members of the 16-bit The processor s resources include seven data types that processor and controller family. Designed using a range from bits to 32-bit long words, and byte and word RISC-like Load/Store architecture, the CPU can operate in strings, plus eight user-selectable addressing modes. The either system or normal modes, permitting privileged nine basic instruction types can be combined with various operations and improving operating system organization data types and addressing modes to form a powerful set and implementation. of 414 instructions. To boost the main CPU s performance capability, the The extended processing architecture features provide a processor core includes hardwired control and is a modular approach to expanding both the hardware and 16-bit real-time processor functioning at register access software capabilities of the Z16COl/CO2. speeds. Register flexibility is created by grouping or overlapping multiple registers, and by allowing extended Notes: All Signals with a preceding front slash, /, are active Low, e.g.: register file capabilities as the system expands. Easy B/AN (WORD is active Low) /B/W (BYTE is active Low, only). extended register file control is accomplished through a single instruction stream communication. Power connections follow conventional descriptions below: TheCPUsupportsthreetypesof interrupts (non-maskable, vectored, and non-vectored) and four traps (system call, Connection Circuit Device extended process architecture instruction, privileged Power V cc DO instructions, and segmentation trap). The vectored and Ground GND ss non-vectored interrupts are maskable. cPs95scc0103 (3/95) 1 216CWCO2 +- ~ziLfli5 cPs95sccolo3 GENERAL DESCRIPTION (Continued) Z-Bus internal Data Bus Z-Bus Interface 0 Z16COO CPU Functional Block Diagram AD13 c) AD14 c) AD13 c) AD12 c) AD11 c) REAMWRITE AD10 c) hwlM4u/sYsTEM ADi ,- BYTEWORD AM).- 3laius AD ,c) ~573 A06 .- ~ ST2 zid~i A& - ST1 YBw AM .- 3m A03 .- IWAlT A02 .- AD1 ,- /STOP AW - : sN4 iNMI : sN2 lnlemlpN M : sN2 INVI : SNl Z16COVCO2 Signal Descriptions 2