APRIL2009 AS6C62256A 32KX8BITLOWPOWERCMOSSRAM FEATURES DESCRIPTION The Read cycle is finished by the 32768x8 bit static CMOS RAM The AS6C62256A is a static RAM falling edge of W, or by the rising Access times 70 ns manufactured using a CMOS edge of E, respectively. process technology with the Common data inputs and data following operating modes: outputs Data retention is guaranteed down - Read - Standby Three-state outputs to 2 V. With the exception of E, all - Write - Data Retention Typ. operating supply current inputs consist of NOR gates, so that The memory array is based on a 6- o 70 ns: 50 mA no pull-up/pull-down resistors are transistor cell. TTL/CMOS-compatible required. Automatical reduction of power The circuit is activated by the falling dissipation in long Read Cycles edge of E. The address and control Power supply voltage 5V + 10% inputs open simultaneously. Operating temperature ranges According to the information of W o 0 to 70 C and G, the data inputs, or outputs, o -40 to 85 C are active. In a Read cycle, the data QS 9000 Quality Standard outputs are activated by the falling ESD protection > 2000 V edge of G, afterwards the data word (MIL STD 883C M3015.7) read will be available at the outputs Latch-up immunity >100 mA DQ0-DQ7. After the address Packages: PDIP28 (600 mil) change, the data outputs go High-Z SOP28 (330 mil) until the new information read is available. The data outputs have not preferred state. PINCONFIGURATION PINDESCRIPTION APRIL/2009 ALLIANCEMEMORY PAGE1of10APRIL2009 AS6C62256A 32KX8BITLOWPOWERCMOSSRAM APRIL/2009 ALLIANCEMEMORY PAGE2of10