September 2006 AS7C1024C Advance Information 5V 128K X 8 CMOS SRAM Features o o 32-pin JEDEC standard packages Industrial (-40 to 85 C) temperature -300 mil SOJ Organization: 131,072 x 8 bits -400 mil SOJ High speed ESD protection 2000 volts - 12 ns address access time - 6 ns output enable access time Low power consumption via chip deselect Easy memory expansion with CE1, CE2, OE inputs TTL/LVTTL-compatible, three-state I/O Pin arrangement Logic block diagram 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) V CC NC 1 32 V GND CC A15 A16 2 31 CE2 A14 3 30 Input buffer A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A0 A5 7 26 A9 A1 I/O7 A11 A4 8 25 A2 A3 9 24 OE 131,702 x 8 A10 A2 10 23 A3 A1 11 22 CE1 A4 Array A0 12 21 I/O7 A5 I/O0 13 20 I/O6 (1,048,576) A6 I/O1 14 19 I/O5 A7 I/O0 I/O2 15 18 I/O4 A8 GND 16 17 I/O3 WE Address decoder Control OE circuit CE1 CE2 12/5/06, v. 1.0 Alliance Memory P. 1 of 9 Copyright Alliance Memory All rights reserved. Address decoder A9 A10 A11 A12 A13 A14 A15 A16 Sense amp AS7C1024CAS7C1024C Functional description The AS7C1024C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 12 ns with output enable access times (t ) of 6 ns are ideal for high AA RC WC OE performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume I SB power. If the bus is static, then full standby power is reached (I ). SB1 A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.50 +7.0 V CC t1 Voltage on any pin relative to GND V 0.50 V +0.50 V t2 CC Power dissipation P 1.25 W D Storage temperature (plastic) T 55 +125 C stg Ambient temperature with V applied T 55 +125 C CC bias DC current into outputs (low) I 50 mA OUT Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE1 CE2 WE OE Data Mode H X X X High Z Standby (I , I ) SB SB1 X L X X High Z Standby (I , I ) SB SB1 L H H H High Z Output disable (I ) CC LH H L D Read (I ) OUT CC LH L X D Write ( ) IN ICC Key: X = dont care, L = low, H = high. 12/5/06, v. 1.0 Alliance Memory P. 2 of 9