March 2004 AS7C1026B 5 V 64K X 16 CMOS SRAM TTL-compatible, three-state I/O Features JEDEC standard packaging Industrial and commercial versions - 44-pin 400 mil SOJ Organization: 65,536 words 16 bits - 44-pin TSOP 2-400 Center power and ground pins for low noise ESD protection 2000 volts High speed Latch-up current 200 mA - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time Low power consumption: ACTIVE - 605 mW / max 10 ns Pin arrangement Low power consumption: STANDBY - 55 mW / max CMOS I/O 44-Pin SOJ (400 mil), TSOP 2 6 T 0.18 u CMOS technology Easy memory expansion with CE, OE inputs 1 A5 A4 44 A3 2 43 A6 Logic block diagram 3 42 A7 A2 4 41 OE A1 A0 A0 5 40 UB 6 39 LB CE A1 V CC 7 38 I/O15 I/O0 A2 64 K 16 I/O1 8 37 I/O14 GND A3 9 36 I/O13 I/O2 Array 10 35 I/O12 I/O3 A4 V 11 34 GND CC A5 12 33 V GND CC A6 13 32 I/O11 I/O4 I/O5 14 31 I/O10 A7 15 30 I/O9 I/O6 16 29 I/O8 I/O7 I/O0I/O7 I/O Control circuit WE 17 28 NC buffer I/O8I/O15 A15 18 27 A8 19 26 A9 A14 20 25 A10 A13 Column decoder WE A12 21 24 A11 22 23 NC NC UB OE LB CE Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 56 78 ns Maximum operating current 110 100 90 80 mA Maximum CMOS standby current 10 10 10 10 mA 3/26/04, v 1.3 Alliance Semiconductor P. 1 of 10 Copyright Alliance Semiconductor. All rights reserved. Row decoder A8 A9 A10 A11 A12 A13 A14 A15 AS7C1026BAS7C1026B Functional description The AS7C1026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5, 6, 7, 8 ns are ideal for AA RC WC OE high-performance applications. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume I power. If the bus is static, then full SB standby power is reached (I ). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions. SB1 A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The device is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.50 +7.0 V CC t1 Voltage on any pin relative to GND V 0.50 V +0.50 V t2 CC Power dissipation P 1.0 W D Storage temperature (plastic) T 65 +150 C stg Ambient temperature with VCC T 55 +125 C bias applied DC current into outputs (low) I 20 mA OUT Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0I/O7 I/O8I/O15 Mode H XXXX High Z High Z Standby (I ), I ) SB SBI LHL L H D High Z Read I/O0I/O7 (I ) OUT CC LHLHL High Z D Read I/O8I/O15 (I OUT CC) LHL L L D D Read I/O0I/O15 (I ) OUT OUT CC LL X L L D D Write I/O0I/O15 (I ) IN IN CC LL X L H D High Z Write I/O0I/O7 (I ) IN CC LL X H L High Z D Write I/O8I/O15 (I ) IN CC L H H X X High Z High Z Output disable (I ) CC L X X H H Key: H = high, L = low, X = dont care. 3/26/04, v 1.3 Alliance Semiconductor P. 2 of 10