September 2006 AS7C1026C A 5 V 64K X 16 CMOS SRAM Features o o Industrial (-40 to 85 C) temperature JEDEC standard packaging - 44-pin 400 mil SOJ Organization: 65,536 words 16 bits - 44-pin TSOP 2-400 Center power and ground pins for low noise ESD protection > 2000 volts High speed - 15 ns address access time - 6 ns output enable access time Low power consumption via chip deselect Easy memory expansion with CE, OE inputs Pin arrangement TTL-compatible, three-state I/O Upper and Lower byte pin 44-Pin SOJ (400 mil), TSOP 2 A4 1 44 A5 2 43 A6 A3 Logic block diagram 3 42 A7 A2 A1 4 41 OE A0 A0 5 40 UB 6 39 LB CE A1 V CC 7 38 I/O15 I/O0 A2 65,536 x 16 I/O1 8 37 I/O14 GND A3 9 36 I/O13 I/O2 Array 10 35 I/O12 I/O3 A4 11 34 GND V CC A5 GND 12 33 V CC A6 13 32 I/O11 I/O4 14 31 I/O10 I/O5 A7 I/O6 15 30 I/O9 I/O7 16 29 I/O8 I/O0I/O7 I/O Control circuit 17 28 NC WE buffer I/O8I/O15 18 27 A8 A15 A14 19 26 A9 20 25 A10 A13 Address decoder WE 21 24 A11 A12 NC 22 23 NC UB OE LB CE 12/5/06, v 1.0 Alliance Memory P. 1 of 9 Copyright Alliance Memory. All rights reserved. Address decoder A8 A9 A10 A11 A12 A13 A14 A15 A S 7C 1 02 6CAS7C1026C Functional description The AS7C1026C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 15 ns with output enable access times (t ) of 6 ns are ideal for high- AA RC WC OE performance applications. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume I power. If the bus is SB static, then full standby power is reached (I ). SB1 A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1026C is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.50 +7.0 V CC t1 Voltage on any pin relative to GND V 0.50 V +0.50 V t2 CC Power dissipation P 1.25 W D Storage temperature (plastic) T 55 +125 C stg Ambient temperature with VCC applied T 55 +125 C bias DC current into outputs (low) I 50 mA OUT Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0I/O7 I/O8I/O15 Mode H X X X X High Z High Z Standby (I ), I ) SB SBI L H L L H D High Z Read I/O0I/O7 (I ) OUT CC L H L H L High Z D Read I/O8I/O15 (I OUT CC) L H L L L D D Read I/O0I/O15 (I ) OUT OUT CC L L X L L D D Write I/O0I/O15 (I ) IN IN CC L L X L H D High Z Write I/O0I/O7 (I ) IN CC L L X H L High Z D Write I/O8I/O15 (I ) IN CC L H H X X High Z High Z Output disable (I ) CC L X X H H Key: H = high, L = low, X = dont care. 12/5/06, v 1.0 Alliance Memory P. 2 of 9