September 2004 AS7C256A 5V 32K X 8 CMOS SRAM (Common I/O) Features TTL-compatible, three-state I/O Pin compatible with AS7C256 28-pin JEDEC standard packages Industrial and commercial temperature options - 300 mil SOJ Organization: 32,768 words 8 bits -8 13.4 mm TSOP 1 High speed ESD protection 2000 volts - 10/12/15/20 ns address access time Latch-up current 200 mA - 5, 6, 7, 8 ns output enable access time 2.0V Data retention Very low power consumption: ACTIVE - 412.5 mW max 10 ns Very low power consumption: STANDBY - 11 mW max CMOS I/O Easy memory expansion with CE and OE inputs Logic block diagram Pin arrangement V 28-pin TSOP 1 (813.4 mm) 28-pin SOJ (300 mil) CC GND Input buffer A14 1 28 V CC A12 2 27 WE OE 1 28 A10 A11 2 CE 27 A7 3 26 A13 A9 3 I/O7 26 A0 A6 4 25 A8 A8 4 25 I/O6 I/O7 A1 A13 5 24 I/O5 A5 5 24 A9 WE 6 23 I/O4 A2 256 X 128 X 8 A4 6 23 A11 V 7 I/O3 22 CC 8 A3 A14 AS7C256A 21 GND A3 7 22 OE Array A12 9 20 I/O2 A2 8 21 A10 A4 10 19 A7 I/O1 11 A1 9 20 CE (262,144) A6 18 I/O0 A5 12 A5 17 A0 A0 10 19 I/O7 A6 16 A4 13 A1 I/O0 15 I/O0 11 18 I/O6 A3 14 A2 A7 I/O1 12 17 I/O5 16 I/O2 13 I/O4 15 GND 14 I/O3 WE Column decoder Control OE circuit CE A A A A A A A 8 9 10 11 12 13 14 Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns Maximum operating current 75 70 65 60 mA Maximum CMOS standby current 2 2 2 2 mA 9/24/04 v.1.2 Alliance Semiconductor P. 1 of 9 Copyright Alliance Semiconductor. All rights reserved. Row decoder Sense amp AS7C256AAS7C256A Functional description The AS7C256A is a 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words 8 bits. It is designed for memory applications requiring fast data access at low voltage, including TM TM Pentium , PowerPC , and portable computing. Alliances advanced circuit design and process techniques permit 5.0V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. CMOS standby mode consumes 11 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5, 6, 7, 8 ns AA RC WC OE are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 0.5V supply. The AS7C256A is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.5 +7.0 V CC t1 Voltage on any pin relative to GND V 0.5 V + 0.5 V t2 CC Power dissipation P 1.0 W D o Storage temperature (plastic) T 65 +150 C stg o Ambient temperature with V applied T 55 +125 C CC bias DC current into outputs (low) I 20 mA OUT Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (I , I ) SB SB1 L H H High Z Output disable (I ) CC LHL D Read (I ) OUT CC LL X D Write (I ) IN CC Key: X = Dont care, L = Low, H = High 9/24/04 v.1.2 Alliance Semiconductor P. 2 of 9