September 2006 AS7C256B A 5V 32K X 8 CMOS SRAM (Common I/O) Features o o Industrial (-40 to 85 C) temperature 28-pin JEDEC standard packages - 300 mil SOJ Organization: 32,768 words 8 bits -8 13.4 mm TSOP High speed - 300 mil PDIP - 15 ns address access time ESD protection 2000 volts - 6 ns output enable access time Low power consumption via chip deselect One chip select plus one Output Enable pin Bidirectional data inputs and outputs TTL-compatible Logic block diagram Pin arrangement 28-pin DIP, SOJ (300 mil) A14 1 28 V CC V CC A12 2 27 WE A7 3 26 A13 GND A6 4 25 A8 A5 5 24 A9 Input buffer A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 A0 10 19 I/O7 I/O7 A1 I/O0 11 18 I/O6 A2 I/O1 32,768 X 8 12 17 I/O5 16 A3 I/O2 13 I/O4 Array 15 GND 14 I/O3 A4 (262,144) A5 28-pin TSOP 1 (813.4mm) A6 I/O0 A7 OE 1 (22) (21) 28 A10 A11 2 CE (23) (20) 27 A9 3 I/O7 (24) (19) 26 A8 4 (25) (18) 25 I/O6 WE A13 5 (26) (17) 24 I/O5 Address decoder WE 6 (27) (16) 23 I/O4 Control V 7 I/O3 (28) (15) 22 OE CC AS7C256B 8 A14 (1) (14) 21 GND circuit 9 (2) (13) 20 A12 I/O2 CE A7 10 (3) (12) 19 I/O1 A6 11 (4) (11) 18 I/O0 A A A A A A A 12 A5 (5) (10) 17 A0 8 9 10 11 12 13 14 13 (6) (9) 16 A4 A1 14 (7) (8) 15 A3 A2 Note: This part is compatible with both pin numbering conventions used by various manufacturers. 12/5/06 V.1.0 Alliance Memory P. 1 of 8 Copyright Alliance Memory. All rights reserved. Address decoder Sense amp AS7C256BAS7C256B Functional description The AS7C256B is a 5V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as TM 32,768 words 8 bits. It is designed for memory applications requiring fast data access at low voltage, including Pentium , TM PowerPC , and port able computing. Alliances advanced circuidesit gn and process techniques permit 5.0V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. Equal address access and cycle times (t , t , t ) of 12 ns with output AA RC WC enable access times (t ) of 6 ns are ideal for high-performance applications. The chip enable ( CE) input permits easy memory OE expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 5.00.5V supply. The AS7C256B is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.5 +7.0 V CC t1 Voltage on any pin relative to GND V 0.5 V + 0.5 V t2 CC Power dissipation P 1.25 W D o Storage temperature (plastic) T 55 +125 C stg o Ambient temperature with V applied T 55 +125 C CC bias DC current into outputs (low) I 50 mA OUT Note: Stresses greater than those listed underAbsolu te Maximum Ratings may cause permanent damage to the device. This is a stress ratin g only and functional operation of the device at these or any other conditions outside those indicated in th e operational sections of this specificaiont is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (I , I ) SB SB1 L H H High Z Output disable (I ) CC LH L D Read (I ) OUT CC LL X D Write (I ) IN CC Notes: H = V , L = V , x = Dont care. IH IL V = 0.2V, V = V - 0.2V. LC HC CC Other inputs V or V . HC LC 12/5/06 V.1.0 Alliance Memory P. 2 of 8