March 2004 AS7C31025B 3.3V 128K X 8 CMOS SRAM (Center power and ground) Features Industrial and commercial temperatures Easy memory expansion with CE, OE inputs Organization: 131,072 x 8 bits Center power and ground High speed TTL/LVTTL-compatible, three-state I/O - 10/12/15/20 ns address access time JEDEC-standard packages - 5, 6, 7, 8 ns output enable access time - 32-pin, 300 mil SOJ Low power consumption: ACTIVE - 32-pin, 400 mil SOJ - 252 mW / max 10 ns ESD protection 2000 volts Low power consumption: STANDBY Latch-up current 200 mA - 18 mW / max CMOS 6 T 0.18 u CMOS technology Pin arrangement Logic block diagram V CC 32-pin SOJ (300 mil) GND 32-pin SOJ (400 mil) Input buffer A16 A0 1 32 A1 2 31 A15 A2 3 30 A14 A0 A3 4 29 A13 A1 I/O7 CE 5 28 OE A2 I/O0 6 512 x 256 x 8 27 I/O7 A3 I/O1 7 26 I/O6 Array A4 V 8 25 CC GND A5 (1,048,576) V GND 9 24 CC A6 I/O2 10 23 I/O5 22 A7 I/O4 I/O0 I/O3 11 A8 21 A12 WE 12 20 A11 A4 13 19 A10 A5 14 WE A6 15 18 A9 Control A7 16 17 A8 Column decoder OE circuit CE Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5678 ns Maximum operating current 70 65 60 55 mA Maximum CMOS standby current 5555 mA 3/24/04, v. 1.3 Alliance Semiconductor P. 1 of 9 Copyright Alliance Semiconductor. All rights reserved. Row decoder A9 A10 A11 A12 A13 A14 A15 A16 Sense amp AS7C31025BAS7C31025B Functional description The AS7C31025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5, 6, 7, 8 ns are ideal for AA RC WC OE high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems. When CE is high the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025B is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.50 +5.0 V CC t1 Voltage on any pin relative to GND V 0.50 V + 0.5 V t2 CC Power dissipation P 1.0 W D o Storage temperature (plastic) T 65 +150 C stg o Ambient temperature with V applied T 55 +125 C CC bias DC current into outputs (low) I 20 mA OUT NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (I , I ) SB SB1 L H H High Z Output disable (I ) CC LHL D Read (I ) OUT CC LL X D Write (I ) IN CC Key: X = dont care, L = low, H = high. 3/24/04, v. 1.3 Alliance Semiconductor P. 2 of 9