March 2004 AS7C31026B 3.3 V 64K X 16 CMOS SRAM Features Industrial and commercial versions Easy memory expansion with CE, OE inputs Organization: 65,536 words 16 bits TTL-compatible, three-state I/O Center power and ground pins for low noise JEDEC standard packaging High speed - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 - 10/12/15/20 ns address access time ESD protection 2000 volts - 5, 6, 7, 8 ns output enable access time Latch-up current 200 mA Low power consumption: ACTIVE - 288 mW / max 10 ns Low power consumption: STANDBY - 18 mW / max CMOS I/O 6 T 0.18 u CMOS technology Logic block diagram Pin arrangement A0 A1 44-Pin SOJ (400 mil), TSOP 2 V CC A2 64 K 16 GND A3 Array A4 1 44 A5 A4 2 43 A6 A3 A5 3 42 A7 A2 A1 4 41 OE A6 5 40 UB A0 A7 6 39 LB CE I/O15 I/O0 7 38 I/O0I/O7 I/O I/O1 8 37 I/O14 Control circuit buffer I/O8I/O15 9 36 I/O13 I/O2 10 35 I/O12 I/O3 V 11 34 GND CC Column decoder WE 12 33 V GND CC 13 32 I/O11 I/O4 I/O5 14 31 I/O10 15 30 I/O9 I/O6 16 29 I/O8 I/O7 UB WE 17 28 NC 18 27 A8 A15 OE 19 26 A9 A14 LB A13 20 25 A10 21 24 A11 A12 CE 22 23 NC NC Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 56 7 8 ns Maximum operating current 80 75 70 65 mA Maximum CMOS standby current 55 5 5 mA 3/26/04, v 1.3 Alliance Semiconductor P. 1 of 10 Copyright Alliance Semiconductor. All rights reserved. Row decoder A8 A9 A10 A11 A12 A13 A14 A15 AS7C31026BAS7C31026B Functional description The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5, 6, 7, 8 ns are ideal for AA RC WC OE high-performance applications. When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The device is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.50 +5.0 V CC t1 Voltage on any pin relative to GND V 0.50 V +0.50 V t2 CC Power dissipation P 1.0 W D Storage temperature (plastic) T 65 +150 C stg Ambient temperature with VCC applied T 55 +125 C bias DC current into outputs (low) I 20 mA OUT Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0I/O7 I/O8I/O15 Mode H X X X X High Z High Z Standby (I ), I ) SB SBI LH L L H D High Z Read I/O0I/O7 (I ) OUT CC L H L H L High Z D Read I/O8I/O15 (I OUT CC) L H LLL D D Read I/O0I/O15 (I ) OUT OUT CC LL X L L D D Write I/O0I/O15 (I ) IN IN CC LL X L H D High Z Write I/O0I/O7 (I ) IN CC L L X H L High Z D Write I/O8I/O15 (I ) IN CC L H H X X High Z High Z Output disable (I ) CC L X X H H Key: H = high, L = low, X = dont care. 3/26/04, v 1.3 Alliance Semiconductor P. 2 of 10