AS7C34098A August 2004 3.3 V 256 K 16 CMOS SRAM Features Pin compatible with AS7C34098 Easy memory expansion with CE, OE inputs Industrial and commercial temperature TTL- and CMOS-compatible, three-state I/O Organization: 262,144 words 16 bits JEDEC standard packages Center power and ground pins - 44-pin SOJ -400-mil High speed - 44-pin TSOP 2 - 48-pin Mini BGA - 10/12/15/20 ns address access time ESD protection 2000 volts - 4/5/6/7 ns output enable access time Low power consumption: ACTIVE Latch-up current 200 mA - 650 mW /max 10 ns Low power consumption: STANDBY - 28.8 mW /max CMOS Individual byte read/write controls Logic block diagram Pin arrangement for SOJ Bottom View 48BGA and TSOP 2 Selection guide 10 12 15 20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 4 5 6 7 ns Industrial 180 160 140 110 mA Maximum operating current Commercial 170 150 130 100 mA Maximum CMOS standby current 8 8 8 8 mA 11/14/11, v. 2.2 Alliance Memory Inc. P. 1 of 11 Copyright Alliance Memory Inc. All rights reserved. AS7C34098A Functional description The AS7C34098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 4/5/6/7 ns are AA RC WC OE ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1 I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1 I/O8, and UB controls the higher bits, I/O9 I/O16. All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C34098A) supply. The device is available in the JEDEC standard 400-mil, 44-pin SOJ, TSOP 2. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND 0.50 +5.0 V V CC t1 Voltage on any pin relative to GND 0.50 V +0.50 V V CC t2 Power dissipation P 1.5 W D Storage temperature (plastic) 65 +150 C T stg Ambient temperature with V applied 55 +125 C T CC bias DC current into outputs (low) 20 mA I OUT Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O1I/O8 I/O9 I/O16 Mode H X X X X High Z High Z Standby (I , I ) SB SB1 L H H X X High Z High Z Output disable (I ) CC L X X H H L H D High Z OUT L H L H L High Z D Read (I ) OUT CC L L D D OUT OUT L H D High Z IN L L X H L High Z D IN L L D D Write (I ) IN IN CC Key: X = Dont care, L = Low, H = High. 11/14/11,v. 2.2 Alliance Memory Inc P. 2 of 11