256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs AS8C803601 ZBT Feature AS8C801801 3.3V I/O, Burst Counter Pipelined Outputs Address and control signals are applied to the SRAM during one clock Features cycle, and two cycles later the associated data cycle occurs, be it rea d or write. 256K x 36, 512K x 18 memory configurations The AS8C803601/801801 contain data I/O, address and control signal Supports high performance system speed - 150MHz registers. Output enable is the only asynchronou s signal and can be (3.8ns Clock-to-Data Access) TM used to disable the outputs at any given time. ZBT Feature - No dead cycles between write and read cycles A Clock Enable ( CEN ) pin allows operation of the to AS8C803601/ 801801 Internally synchronized output buffer enable eliminates the be suspended as long as necessary. All synchronous inputs are ignored when need to control OE (CEN)is high and the internal device registers will hold their previous values. Single R/W (READ/WRITE) control pin There are three chip enable pins (CE1, CE2, CE2) that allow the user Positive clock-edge triggered address, data, and control to deselect the device when desired. If any one of these three are not asserted signal registers for fully pipelined applications when ADV/LD is low, no new memory operation can be initiated. However, 4-word burst capability (interleaved or linear) any pending data transfers (reads or writes) will be completed. The data bus Individual byte write (BW1 - BW4) control (May tie active) will tri-state two cycles after chip is deselected or a write is initiated. Three chip enables for simple depth expansion TheAS8C803601/801801 have an on-chip burst counter. In the burst 3.3V power supply (5%) mode,the AS8C803601/801801 can provide fourcycles of data for a single 3.3V I/O Supply (VDDQ) address presented to the SRAM. The order of the burst sequence is Power down controlled by ZZ input defined by the LBO input pin. The LBO pin selects between linear and Packaged in a JEDEC standard 100-pin plastic thin quad interleaved burst sequence. The ADV/LD signal is used to load a new flatpack (TQFP). external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). Description The AS8C803601/801801 SRAM utilize IDT s latest high-performance The AS8C803601/801801 are3.3V high-speed 9,437,184 bit CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100- (9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus pin thin plastic quad flatpack (TQFP) . cycles when turning the bus around between reads and writes, or writes and TM reads. Thus, they have been given the name ZBT , or Zero Bus Turnaround. Pin Description Summary A0-A18 Address Inputs Input Synchronous CE1, CE2, CE2 Chip Enables Input Synchronous Output Enable Input Asynchronous OE R/W Read/Write S ignal Input Synchronous Clock Enable Input Synchronous CEN BW1, BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/LD Advance burst address / Load new address Input Synchronous Linear / Interleaved Burst Order Input Static LBO ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5304 tbl 01 SEPTEMBER 2010 1 DSC-5304/07AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial TemperatureRange (1) Pin Definitions Symbol Pin Function I/O Active Description A0-A18 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADVLD/ is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is s ampled high. R/W Read / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place two clock cycles later. CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. Individual Byte I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. BW1-BW4 Write Enables On load write cycles (When RW/ and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device two cycles later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. Chip Enables I LOW Synchronous active low chip enable.CE 1 and CE2 are used with CE2 to e nable the AS8C CE1, CE2 803601/ 801801 (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the TM rising edge of clock, initiates a deselect cycle. The ZBT has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated. CE2 Chip Enable I HIGH Synchronous active high chip enable. C2E is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2. CLK Clock I N/A This is the clock input to theAS8C803601/801801. Except for OE, all timing references for the device are made with respect to the rsi ing edge of CLK. I/O0-I/O31 Data Inp ut/Output I/O N/A Synchronous data input/output (I/O) p ins. Both the d ata input path and data output p ath are I/OP1-I/OP4 registered and triggered by the rising edge of CLK. Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. LBO When LBO is low the Linear burst sequence is selected. LBO is a static input and it must not change during device operation. Output Enable I LOW Asynchronous output enable.OEmust be low to readdata fromtheAS8C803601/801801.When OE OE is high the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied low. ZZ Sleep Mode I N/A Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the AS8C803601/801801to its lowest power consumption level.Data retention is guaranteed in Sleep Mode. VDD Power Supply N/A N/A 3.3V core power supply. VDDQ Power Supply N/A N/A 3.3V I/O Supply. VSS Ground N/A N/A Ground. 5304tbl 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.422