256K X 36, 512K X 18 3.3V Synchronous SRAMs AS8C803600 3.3V I/O, Burst Counter AS8C801800 Pipelined Outputs, Single Cycle Deselect Features 256K x 36 / 512K x 18. The SRAMs contain write, data, 256K x 36, 512K x 18 memory configurations address and control registers. Internal logic allows the SRAM to Supports high system speed: generate a self-timed write based upon a decision which can be left until the end of the write cycle. 150MHz 3.8ns clock access time The burst mode feature offers the highest level of performance to the system designer, as the AS8C803600/801800 can provide four cycles of LBO input selects interleaved or linear burst mode data for a single address presented to the SRAM. An internal burst address Self-timed write cycle with global write control (GW), byte counter accepts the first cycle address from the processor, initiating the write enable (BWE), and byte writes (BWx) access sequence. The first cycle of output data will be pipelined for one 3.3V core power supply cycle before it is available on the next rising clock edge. If burst mode Power down controlled by ZZ input operation is selected (ADV=LOW), the subsequent three cycles of output 3.3V I/O supply (VDDQ) data will be available to the user on the next three rising clock edges. The Packaged in a JEDEC Standard 100-pin thin plastic quad order of these three addresses are defined by the internal burst counter flatpack (TQFP) and the LBO input pin. The AS8C803600/801800 SRAMs utilize the latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100- Description pin thin plastic quad flatpack (TQFP), The AS8C803600/801800 are high-speed SRAMs organized as Pin Description Summary A0-A18 Address Inputs Input Synchronous Chip Enable Input Synchronous CE CS0, CS1 Chip Selects Input Synchronous Output Enable Input Asynchronous OE Global Write Enable Input Synchronous GW BWE Byte Write Enable Input Synchronous (1) Individual Byte Write Selects Input Synchronous BW1, BW2, BW3, BW4 CLK Clock Input N/A ADV Burst Address Advance Input Synchronous Address Status (Cache Controller) Input Synchronous ADSC Address Status (Processor) Input Synchronous ADSP Linear / Interleaved Burst Order Input DC LBO ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A NOTE: 5310 tbl 01 1. BW3 and BW4 are not applicable for other devices September 2010 1 . AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial Temperature Range (1) Pin Definitions Symbol Pin Function I/O Active Description A0-A18 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK and ADSC Low or ADSP Low and CE Low. Address Status I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is ADSC (Cache Controller) used to load the address registers with new addresses. Address Status I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is used to ADSP (Processor) load the address registers with new addresses. ADSP is gated by CE. Burst Address I LOW Synchronous Address Advance. ADV is an active LOW input that is used to advance the ADV Advance internal burst counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not incremented that is, there is no address advance. BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle. Individual Byte I LOW Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. BW1-BW4 Write Enables Any active byte write causes all outputs to be disabled. Chip Enable I LOW Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V67603/7803. CE CE also gates ADSP. CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this input. CS0 Chip Select 0 I HIGH Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip. Chip Select 1 I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip. CS1 Global Write I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW GW Enable on the rising edge of CLK. GW supersedes individual byte write enables. I/O0-I/O31 Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are I/OP1-I/OP4 registered and triggered by the rising edge of CLK. Linear Burst Order I LOW Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst LBO sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state while the device is operating. OE Output Enable I LOW Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high- impedance state. VDD Power Supply N/A N/A 3.3V core power supply. VDDQ Power Supply N/A N/A 3.3V I/O Supply. VSS Ground N/A N/A Ground. NC No Connect N/A N/A NC pins are not electrically connected to the device. ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the AS8C803600/1800 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode. 5310 tbl 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.422