19-5580 Rev 10/10 DS1220AB/AD 16k Nonvolatile SRAM www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the A7 VCC 1 24 absence of external power A6 23 A8 2 A5 A9 Data is automatically protected during power 3 22 A4 4 21 WE loss A3 OE 20 5 Directly replaces 2k x 8 volatile static RAM A2 19 A10 6 A1 or EEPROM CE 18 7 A0 17 DQ7 8 Unlimited write cycles DQ0 DQ6 9 16 Low-power CMOS DQ1 10 DQ5 15 JEDEC standard 24-pin DIP package DQ2 11 14 DQ4 Read and write access times of 100 ns 12 GND 13 DQ3 Lithium energy source is electrically 24-Pin ENCAPSULATED PACKAGE disconnected to retain freshness until power 720-mil EXTENDED is applied for the first time Full 10% V operating range (DS1220AD) CC PIN DESCRIPTION Optional 5% V operating range CC A0-A10 - Address Inputs (DS1220AB) DQ0-DQ7 - Data In/Data Out Optional industrial temperature range of -40C to +85C, designated IND - Chip Enable CE - Write Enable WE - Output Enable OE V - Power (+5V) CC GND - Ground DESCRIPTION The DS1220AB and DS1220AD 16k Nonvolatile SRAMs are 16,384-bit, fully static, nonvolatile SRAMs organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors V for an out-of-tolerance condition. When such a condition CC occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs directly conforming to the popular bytewide 24-pin DIP standard. The devices also match the pinout of the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 8 DS1220AB/AD READ MODE The DS1220AB and DS1220AD execute a read cycle whenever (Write Enable) is inactive (high) and WE (Chip Enable) and (Output Enable) are active (low). The unique address specified by the 11 CE OE address inputs (A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within t (Access Time) after the last address input signal is ACC stable, providing that the CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either t for CE or t for OE rather than address access. CO OE WRITE MODE The DS1220AB and DS1220AD execute a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t ) before another cycle can be initiated. The OE control signal should be kept inactive (high) WR during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in t from its falling edge. ODW DATA RETENTION MODE The DS1220AB provides full functional capability for V greater than 4.75 volts and write protects by CC 4.5V. The DS1220AD provides full functional capability for V greater than 4.5 volts and write protects CC by 4.25V. Data is maintained in the absence of V without any additional support circuitry. The CC nonvolatile static RAMs constantly monitor V . Should the supply voltage decay, the NV SRAMs CC automatically write protect themselves, all inputs become dont care, and all outputs become high impedance. As V falls below approximately 3.0 volts, a power switching circuit connects the lithium CC energy source to RAM to retain data. During power-up, when V rises above approximately 3.0 volts, CC the power switching circuit connects external V to RAM and disconnects the lithium energy source. CC Normal RAM operation can resume after V exceeds 4.75 volts for the DS1220AB and 4.5 volts for the CC DS1220AD. FRESHNESS SEAL Each DS1220 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When V is first applied at a level of greater than V , the lithium CC TP energy source is enabled for battery backup operation. 2 of 8