19-5579 Rev 10/10 NOT RECOMMENDED FOR NEW DESIGNS DS1220Y 16k Nonvolatile SRAM www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the A7 VCC 24 absence of external power 1 A6 23 A8 2 Data is automatically protected during power A5 A9 3 22 loss A4 21 WE 4 A3 Directly replaces 2k x 8 volatile static RAM OE 5 20 A2 6 19 A10 or EEPROM A1 18 CE 7 Unlimited write cycles A0 8 17 DQ7 Low-power CMOS DQ0 DQ6 9 16 DQ1 JEDEC standard 24-pin DIP package 10 DQ5 15 DQ2 11 14 DQ4 Read and write access times of 100 ns 12 GND 13 DQ3 Full 10% operating range Optional industrial temperature range of 24-Pin ENCAPSULATED PACKAGE -40C to +85C, designated IND 720-mil EXTENDED PIN DESCRIPTION A0-A10 - Address Inputs DQ0-DQ7 - Data In/Data Out - Chip Enable CE - Write Enable WE OE - Output Enable V - Power (+5V) CC GND - Ground DESCRIPTION The DS1220Y 16k Nonvolatile SRAM is a 16,384-bit, fully static, nonvolatile RAM organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that constantly monitor V for an out-of-tolerance condition. When such a condition occurs, the lithium CC energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAM can be used in place of existing 2k x 8 SRAMs directly conforming to the popular bytewide 24-pin DIP standard. The DS1220Y also matches the pinout of the 2716 EPROM or the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 9 NOT RECOMMENDED FOR NEW DESIGNS DS1220Y READ MODE The DS1220Y executes a read cycle whenever (Write Enable) is inactive (high) and (Chip WE CE Enable) and (Output Enable) are active (low). The unique address specified by the 11 address inputs OE (A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within t (Access Time) after the last address input signal is stable, providing ACC that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either t for CE or CO t for OE rather than address access. OE WRITE MODE The DS1220Y executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WEmust return to the high state for a minimum recovery time (t ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during WR write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in t from its falling edge. ODW DATA RETENTION MODE The DS1220Y provides full-functional capability for V greater than 4.5 volts and write protects at 4.25 CC nominal. Data is maintained in the absence of V without any additional support circuitry. The CC DS1220Y constantly monitors V . Should the supply voltage decay, the NV SRAM automatically write CC protects itself, all inputs become dont care, and all outputs become high-impedance. As V falls CC below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when V rises above approximately 3.0 volts, the power switching circuit CC connects external V to RAM and disconnects the lithium energy source. Normal RAM operation can CC resume after V exceeds 4.5 volts. CC 2 of 9