19-5603 Rev 10/10 NOT RECOMMENDED FOR NEW DESIGNS DS1225Y 64k Nonvolatile SRAM www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the 1 28 VCC NC absence of external power A12 27 WE 2 A7 3 26 NC Data is automatically protected during power 4 25 A8 A6 loss A5 A9 5 24 Directly replaces 2k x 8 volatile static RAM 6 23 A11 A4 or EEPROM OE A3 7 22 A2 8 21 A10 Unlimited write cycles A1 9 20 CE Low-power CMOS A0 10 19 DQ7 JEDEC standard 28-pin DIP package DQ0 DQ6 11 18 12 17 Read and write access times of 150 ns DQ1 DQ5 13 16 DQ4 Full 10% operating range DQ2 14 15 GND DQ3 Optional industrial temperature range of -40C to +85C, designated IND 24-Pin ENCAPSULATED PACKAGE 720-mil EXTENDED PIN DESCRIPTION A0-A12 - Address Inputs DQ0-DQ7 - Data In/Data Out CE - Chip Enable WE - Write Enable OE - Output Enable V - Power (+5V) CC GND - Ground DESCRIPTION The DS1225Y 64k Nonvolatile SRAM is a 65,536-bit, fully static, nonvolatile RAM organized as 8192 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors V for an out-of-tolerance condition. When such a condition occurs, the lithium CC energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAM can be used in place of existing 8k x 8 SRAMs directly conforming to the popular bytewide 28-pin DIP standard. The DS1225Y also matches the pinout of the 2764 EPROM or the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for micro- processor interfacing. 1 of 8 NOT RECOMMENDED FOR NEW DESIGNS DS1225Y READ MODE The DS1225Y executes a read cycle whenever (Write Enable) is inactive (high) and (Chip WE CE Enable) and (Output Enable) are active (low). The unique address specified by the 13 address inputs OE (A -A ) defines which of the 8192 bytes of data is to be accessed. Valid data will be available to the 0 12 eight data output drivers within t (Access Time) after the last address input signal is stable, providing ACC that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either t for CE CO or t for OE rather than address access. OE WRITE MODE The DS1225Y executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of or . All address inputs must be CE WE kept valid throughout the write cycle. must return to the high state for a minimum recovery time WE (t ) before another cycle can be initiated. The control signal should be kept inactive (high) during OE WR write cycles to avoid bus contention. However, if the output drivers are enabled ( and active) then CE OE WE will disable the outputs in t from its falling edge. ODW DATA RETENTION MODE The DS1225Y provides full functional capability for V greater than 4.5 volts and write protects at 4.25 CC nominal. Data is maintained in the absence of V without any additional support circuitry. The CC DS1225Y constantly monitors V . Should the supply voltage decay, the NV SRAM automatically write CC protects itself, all inputs become dont care, and all outputs become high impedance. As V falls CC below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when V rises above approximately 3.0 volts, the power switching circuit CC connects external V to RAM and disconnects the lithium energy source. Normal RAM operation can CC resume after V exceeds 4.5 volts. CC 2 of 8