19-5636 Rev 11/10 DS1230W 3.3V 256k Nonvolatile SRAM www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the V A14 1 28 CC absence of external power A12 27 WE 2 A7 3 26 A13 Data is automatically protected during power 4 25 A8 A6 loss A5 5 24 A9 Replaces 32k x 8 volatile static RAM, A4 6 23 A11 A3 7 22 OE EEPROM or Flash memory A2 8 21 A10 Unlimited write cycles A1 CE 9 20 Low-power CMOS A0 10 19 DQ7 DQ6 Read and write access times of 100ns DQ0 11 18 12 17 DQ1 DQ5 Lithium energy source is electrically 13 16 DQ4 DQ2 disconnected to retain freshness until power is 14 15 GND DQ3 applied for the first time 28-Pin Encapsulated Package Optional industrial temperature range of 740-Mil Extended -40C to +85C, designated IND JEDEC standard 28-pin DIP package 34 1 NC PowerCap Module (PCM) package NC 33 2 NC NC - Directly surface-mountable module 3 32 A14 NC 31 4 A13 NC - Replaceable snap-on PowerCap provides 30 V 5 A12 CC 6 29 A11 WE lithium backup battery 28 7 A10 OE 27 8 A9 - Standardized pinout for all nonvolatile CE 9 26 A8 DQ7 25 10 A7 SRAM products DQ6 24 11 A6 DQ5 - Detachment feature on PowerCap allows 23 12 A5 DQ4 22 A4 13 DQ3 GND V BAT easy removal using a regular screwdriver 21 14 A3 DQ2 15 20 A2 DQ1 19 16 A1 DQ0 18 17 A0 GND 34-Pin PowerCap Module (PCM) (Uses DS9034PC+ or DS9034PCI+ PowerCap) PIN DESCRIPTION A0 - A14 - Address Inputs DQ0 - DQ7 - Data In/Data Out CE - Chip Enable WE - Write Enable OE - Output Enable V - Power (+3.3V) CC GND - Ground NC - No Connect 1 of 10 DS1230W DESCRIPTION The DS1230W 3.3V 256k Nonvolatile SRAM is a 262,144-bit, fully static, nonvolatile SRAM organized as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry, which constantly monitors V for an out-of-tolerance condition. When such a condition occurs, CC the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package DS1230W devices can be used in place of existing 32k x 8 static RAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230W devices in the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete Nonvolatile SRAM Module. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. READ MODE The DS1230W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs (A A ) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the 0 14 eight data output drivers within t (Access Time) after the last address input signal is stable, providing ACC that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either t for CE or t for OE rather than address access. CO OE WRITE MODE The DS1230W executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t ) WR before another cycle can be initiated. The OEcontrol signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in t from its falling edge. ODW DATA RETENTION MODE The DS1230W provides full functional capability for V greater than 3.0 volts and write protects by 2.8 CC volts. Data is maintained in the absence of V without any additional support circuitry. The nonvolatile CC static RAMs constantly monitor V . Should the supply voltage decay, the NV SRAMs automatically CC write protect themselves, all inputs become dont care, and all outputs become high-impedance. As V CC falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when V rises above approximately 2.5 volts, the power CC switching circuit connects external V to RAM and disconnects the lithium energy source. Normal CC RAM operation can resume after V exceeds 3.0 volts. CC FRESHNESS SEAL Each DS1230W device is shipped from Maxim with its lithium energy source disconnected, guaranteeing full energy capacity. When V is first applied at a level greater than 3.0 volts, the lithium energy source CC is enabled for battery back-up operation. 2 of 10