19-5638 Rev 11/10 DS1245Y/AB 1024k Nonvolatile SRAM www .maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the NC 1 32 V CC absence of external power A16 31 A15 2 A14 NC 3 30 Data is automatically protected during power 4 29 A12 WE loss A7 A13 5 28 Replaces 128k x 8 volatile static RAM, A6 6 27 A8 A5 A9 EEPROM or Flash memory 7 26 A11 A4 8 25 Unlimited write cycles A3 OE 9 24 Low-power CMOS A2 10 23 A10 Read and write access times of 70 ns A1 CE 11 22 12 21 A0 DQ7 Lithium energy source is electrically 13 20 DQ6 DQ0 disconnected to retain freshness until power is 14 19 DQ1 DQ5 applied for the first time DQ2 15 18 DQ4 Full 10% V operating range (DS1245Y) CC 17 GND 16 DQ3 Optional 5% V operating range CC 32-Pin Encapsulated Package (DS1245AB) 740-mil Extended Optional industrial temperature range of -40C to +85C, designated IND JEDEC standard 32-pin DIP package 1 34 NC NC 33 2 NC A15 PowerCap Module (PCM) package 32 3 A14 A16 31 4 A13 NC - Directly surface-mountable module 30 5 A12 V CC 6 29 A11 WE - Replaceable snap-on PowerCap provides 28 7 A10 OE 8 27 A9 lithium backup battery CE 26 9 A8 DQ7 25 - Standardized pinout for all nonvolatile 10 A7 DQ6 24 A6 11 DQ5 SRAM products 23 12 A5 DQ4 13 22 A4 DQ3 GND V BAT - Detachment feature on PowerCap allows 14 21 A3 DQ2 20 15 A2 DQ1 easy removal using a regular screwdriver 16 19 A1 DQ0 18 17 A0 GND 34-Pin PowerCap Module (PCM) (Uses DS9034PC+ or DS9034PCI+ PowerCap) PIN DESCRIPTION A0 - A16 - Address Inputs DQ0 - DQ7 - Data In/Data Out CE - Chip Enable WE - Write Enable OE - Output Enable V - Power (+5V) CC GND - Ground NC - No Connect 1 of 10 DS1245Y/AB DESCRIPTION The DS1245 1024k Nonvolatile SRAMs are1,048,576-bit, fully static, nonvolatile SRAMs organized as 131,072 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors V for an out-of-tolerance condition. When such a condition CC occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package DS1245 devices can be used in place of existing 128k x 8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1245 devices in the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. READ MODE The DS1245 executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and (Output Enable) are active (low). The unique address specified by the 17 address inputs (A - OE 0 A ) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the eight 16 data output drivers within t (Access Time) after the last address input signal is stable, providing that ACC CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either t for CE or t for OE rather than address access. CO OE WRITE MODE The DS1245 executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t ) WR before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in t from its falling edge. ODW DATA RETENTION MODE The DS1245AB provides full functional capability for V greater than 4.75 volts and write protects by CC 4.5 volts. The DS1245Y provides full functional capability for V greater than 4.5 volts and write- CC protects by 4.25 volts. Data is maintained in the absence of V without any additional support circuitry. CC The nonvolatile static RAMs constantly monitor V . Should the supply voltage decay, the NV SRAMs CC automatically write-protect themselves, all inputs become dont care, and all outputs become high impedance. As V falls below approximately 3.0 volts, a power switching circuit connects the lithium CC energy source to RAM to retain data. During power-up, when V rises above approximately 3.0 volts, CC the power switching circuit connects external V to RAM and disconnects the lithium energy source. CC Normal RAM operation can resume after V exceeds 4.75 volts for the DS1245AB and 4.5 volts for the CC DS1245Y. FRESHNESS SEAL Each DS1245 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing full energy capacity. When V is first applied at a level greater than 4.25 volts, the lithium energy source CC is enabled for battery back-up operation. 2 of 10