19-5593 Rev 10/10 DS1330Y/AB 256k Nonvolatile SRAM with Battery Monitor www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the absence of external power 34 NC 1 BW 33 2 NC Data is automatically protected during power NC 3 32 A14 NC 31 4 A13 loss RST 30 5 A12 V CC Power supply monitor resets processor when 29 6 A11 WE 7 28 A10 OE V power loss occurs and holds processor in 27 CC 8 A9 CE 9 26 A8 DQ7 reset during V ramp-up CC 25 10 A7 DQ6 24 11 A6 DQ5 Battery monitor checks remaining capacity 23 12 A5 DQ4 22 13 A4 V daily DQ3 GND BAT 21 14 A3 DQ2 Read and write access times of 70ns 15 20 A2 DQ1 19 16 A1 DQ0 Unlimited write cycle endurance 18 A0 17 GND Typical standby current 50A 34-Pin POWERCAP MODULE (PCM) Upgrade for 32k x 8 SRAM, EEPROM or (Uses DS9034PC+ or DS9034PCI+ PowerCap) Flash Lithium battery is electrically disconnected to PIN DESCRIPTION retain freshness until power is applied for the A0 A14 - Address Inputs first time DQ0 DQ7 - Data In/Data Out Full 10% V operating range (DS1330Y) CC - Chip Enable CE or optional 5% V operating range CC - Write Enable WE (DS1330AB) - Output Enable OE Optional industrial temperature range of - Reset Output RST -40C to +85C, designated IND PowerCap Module (PCM) package - Battery Warning BW - Directly surface-mountable module V - Power (+5V) CC - Replaceable snap-on PowerCap provides GND - Ground lithium backup battery NC - No Connect - Standardized pinout for all nonvolatile (NV) SRAM products - Detachment feature on PowerCap allows easy removal using a regular screwdriver DESCRIPTION The DS1330 256k NV SRAMs are 262,144-bit, fully static, NV SRAMs organized as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors V for an out-of-tolerance condition. When such a condition occurs, the lithium energy source CC is automatically switched on and write protection is unconditionally enabled to prevent data corruption. Additionally, the DS1330 devices have dedicated circuitry for monitoring the status of V and the status CC of the internal lithium battery. DS1330 devices in the PowerCap module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete NV SRAM module. The devices can be used in place of 32k x 8 SRAM, EEPROM, or Flash components. 1 of 10 DS1330Y/AB READ MODE The DS1330 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs (A A ) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the 0 14 eight data output drivers within t (Access Time) after the last address input signal is stable, providing ACC that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal ( or ) and the limiting CE OE parameter is either t for CE or t for OE rather than address access. CO OE WRITE MODE The DS1330 devices execute a write cycle whenever the WE and CE signals are in the active (low) state after address inputs are stable. The later-occurring falling edge of or will determine the start of CE WE the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. must return to the high state for a minimum recovery WE time (t ) before another cycle can be initiated. The OE control signal should be kept inactive (high) WR during write cycles to avoid bus contention. However, if the output drivers are enabled ( and CE OE active) then WE will disable the outputs in t from its falling edge. ODW DATA RETENTION MODE The DS1330AB provides full-functional capability for V greater than 4.75V and write protects by CC 4.5V. The DS1330Y provides full-functional capability for V greater than 4.5V and write protects by CC 4.25V. Data is maintained in the absence of V without any additional support circuitry. The NV CC SRAMs constantly monitor V . Should the supply voltage decay, the NV SRAMs automatically write CC protect themselves, all inputs become dont care, and all outputs become high-impedance. As V falls CC below approximately 2.7V, the power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when V rises above approximately 2.7V, the power switching circuit CC connects external V to the RAM and disconnects the lithium energy source. Normal RAM operation CC can resume after V exceeds 4.75V for the DS1330AB and 4.5V for the DS1330Y. CC SYSTEM POWER MONITORING DS1330 devices have the ability to monitor the external V power supply. When an out-of-tolerance CC power supply condition is detected, the NV SRAMs warn a processor-based system of impending power failure by asserting RST. On power-up, RSTis held active for 200ms nominal to prevent system operation during power-on transients and to allow t to elapse. RST has an open drain output driver. REC BATTERY MONITORING The DS1330 devices automatically perform periodic battery voltage monitoring on a 24-hour time interval. Such monitoring begins within t after V rises above V and is suspended when power REC CC TP failure occurs. After each 24-hour period has elapsed, the battery is connected to an internal 1M test resistor for one second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the battery warning output is asserted. Once asserted, remains active until the module is replaced. BW BW The battery is still retested after each V power-up, however, even if BW is active. If the battery voltage CC is found to be higher than 2.6V during such testing, is de-asserted and regular 24-hour testing BW resumes. BW has an open drain output driver. 2 of 10