19-5586 Rev 10/10 DS1350W 3.3V 4096k Nonvolatile SRAM with Battery Monitor www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power BW 1 34 A18 A15 2 33 A17 loss A16 3 32 A14 RST 4 31 A13 Power supply monitor resets processor when V 5 30 A12 CC V power loss occurs and holds processor in CC WE 6 29 A11 OE 7 28 A10 reset during V ramp-up CC CE 8 27 A9 DQ7 9 26 A8 Battery monitor checks remaining capacity DQ6 A7 10 25 daily DQ5 11 24 A6 DQ4 A5 12 23 Read and write access times of 100ns DQ3 A4 13 22 DQ2 A3 14 21 Unlimited write cycle endurance DQ1 A2 15 20 V GND BAT DQ0 A1 16 19 Typical standby current 50 A GND A0 17 18 Upgrade for 512k x 8 SRAM, EEPROM or 34-Pin PowerCap Module (PCM) Flash (Uses DS9034PC+ or DS9034PCI+ PowerCap) Lithium battery is electrically disconnected to retain freshness until power is applied for the PIN DESCRIPTION first time A0-A18 - Address Inputs Optional industrial temperature range of DQ0-DQ7 - Data In/Data Out -40C to +85C, designated IND CE - Chip Enable PowerCap Module (PCM) package WE - Write Enable - Directly surface-mountable module OE - Output Enable - Replaceable snap-on PowerCap provides lithium backup battery RST - Reset Output - Standardized pinout for all nonvolatile BW - Battery Warning Output SRAM products V - Power (+3.3 Volts) CC - Detachment feature on PowerCap allows GND - Ground easy removal using a regular screwdriver NC - No Connect DESCRIPTION The DS1350W 3.3V 4096k Nonvolatile SRAM is a 4,194,304-bit, fully static, nonvolatile SRAM organized as 524,288 words by eight bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors V for an out-of-tolerance condition. When such a CC condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. Additionally, the DS1350W has dedicated circuitry for monitoring the status of V and the status of the internal lithium battery. DS1350W devices in the CC PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete Nonvolatile SRAM module. The devices can be used in place of 512k x 8 SRAM, EEPROM or Flash components. 1 of 10 DS1350W READ MODE The DS1350W executes a read cycle whenever (Write Enable) is inactive (high) and (Chip WE CE Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs (A - A ) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the 0 18 eight data output drivers within t (Access Time) after the last address input signal is stable, providing ACC that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either t for CE or t for OE rather than address access. CO OE WRITE MODE The DS1350W executes a write cycle whenever the WE and CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during WR write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in t from its falling edge. ODW DATA RETENTION MODE The DS1350W provides full functional capability for V greater than 3.0 volts and write protects by 2.8 CC volts. Data is maintained in the absence of V without any additional support circuitry. The nonvolatile CC static RAMs constantly monitor V . Should the supply voltage decay, the NV SRAMs automatically CC write protect themselves, all inputs become dont care, and all outputs become high impedance. As V CC falls below approximately 2.5 volts, the power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when V rises above approximately 2.5 volts, the power CC switching circuit connects external V to the RAM and disconnects the lithium energy source. Normal CC RAM operation can resume after V exceeds 3.0 volts. CC SYSTEM POWER MONITORING The DS1350W has the ability to monitor the external V power supply. When an out-of-tolerance power CC supply condition is detected, the NV SRAM warns a processor-based system of impending power failure by asserting RST . On power-up, RST is held active for 200 ms nominal to prevent system operation during power-on transients and to allow t to elapse. RST has an open-drain output driver. REC BATTERY MONITORING The DS1350W automatically performs periodic battery voltage monitoring on a 24-hour time interval. Such monitoring begins within t after V rises above V and is suspended when power failure REC CC TP occurs. After each 24-hour period has elapsed, the battery is connected to an internal 1 M test resistor for 1 second. During this 1 second, if battery voltage falls below the battery voltage trip point (2.6V), the battery warning output is asserted. Once asserted, remains active until the module is replaced. BW BW The battery is still retested after each V power-up, however, even if is active. If the battery voltage BW CC is found to be higher than 2.6V during such testing, is de-asserted and regular 24-hour testing BW resumes. has an open-drain output driver. BW 2 of 10