19-5585 Rev 10/10 DS1350Y/AB 4096k Nonvolatile SRAM with Battery Monitor www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the absence of external power 34 1 A18 BW 33 2 A17 Data is automatically protected during power A15 3 32 A14 A16 31 4 A13 loss RST 30 5 A12 V CC Power supply monitor resets processor when 6 29 A11 WE 28 7 A10 OE V power loss occurs and holds processor in 27 CC 8 A9 CE 26 9 A8 DQ7 reset during V ramp-up CC 25 10 A7 DQ6 24 11 A6 DQ5 Battery monitor checks remaining capacity 23 12 A5 DQ4 22 13 A4 daily DQ3 GND V BAT 21 14 A3 DQ2 15 20 A2 Read and write access times of 70ns DQ1 19 16 A1 DQ0 Unlimited write cycle endurance 17 18 A0 GND Typical standby current 50A 34-Pin PowerCap Module (PCM) Upgrade for 512k x 8 SRAM, EEPROM, or (Uses DS9034PC+ or DS9034PCI+ PowerCap) Flash Lithium battery is electrically disconnected to retain freshness until power is applied for the PIN DESCRIPTION first time A0 A18 - Address Inputs DQ0 DQ7 - Data In/Data Out Full 10% V operating range (DS1350Y) CC or optional 5% V operating range CE - Chip Enable CC (DS1350AB) WE - Write Enable Optional industrial temperature range of OE - Output Enable -40C to +85C, designated IND RST - Reset Output PowerCap Module (PCM) package BW - Battery Warning - Directly surface-mountable module V - Power (+5V) CC - Replaceable snap-on PowerCap provides GND - Ground lithium backup battery - Standardized pinout for all nonvolatile (NV) SRAM products - Detachment feature on PowerCap allows easy removal using a regular screwdriver DESCRIPTION The DS1350 4096k NV SRAMs are 4,194,304 bit, fully static, NV SRAMs organized as 524,288 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry, which constantly monitors V for an out-of-tolerance condition. When such a condition occurs, the lithium CC energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. Additionally, the DS1350 devices have dedicated circuitry for monitoring the status of V and the status of the internal lithium battery. DS1350 devices in the PowerCap Module package are CC directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete NV SRAM module. The devices can be used in place of 512k x 8 SRAM, EEPROM or Flash components. 1 of 10 DS1350Y/AB READ MODE The DS1350 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and (Output Enable) are active (low). The unique address specified by the 19 address inputs OE (A -A ) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the 0 18 eight data output drivers within t (Access Time) after the last address input signal is stable, providing ACC that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either t for CE or t for OE rather than address access. CO OE WRITE MODE The DS1350 devices execute a write cycle whenever the WE and CE signals are in the active (low) state after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t ) before another cycle can be initiated. The OE control signal should be kept inactive (high) WR during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in t from its falling edge. ODW DATA RETENTION MODE The DS1350AB provides full functional capability for V greater than 4.75V and write protects by 4.5V. CC The DS1350Y provides full functional capability for V greater than 4.5V and write protects by 4.25V. CC Data is maintained in the absence of V without any additional support circuitry. The NV SRAMs CC constantly monitor V . Should the supply voltage decay, the NV SRAMs automatically write protect CC themselves, all inputs become dont care, and all outputs become high-impedance. As V falls below CC approximately 2.7V, the power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when V rises above approximately 2.7V, the power switching circuit connects CC external V to the RAM and disconnects the lithium energy source. Normal RAM operation can resume CC after V exceeds 4.75V for the DS1350AB and 4.5V for the DS1350Y. CC SYSTEM POWER MONITORING DS1350 devices have the ability to monitor the external V power supply. When an out-of-tolerance CC power supply condition is detected, the NV SRAMs warn a processor-based system of impending power failure by asserting RST. On power-up, RST is held active for 200ms nominal to prevent system operation during power-on transients and to allow t to elapse. has an open drain output driver. RST REC BATTERY MONITORING The DS1350 devices automatically perform periodic battery voltage monitoring on a 24-hour time interval. Such monitoring begins within t after V rises above V and is suspended when power REC CC TP failure occurs. After each 24-hour period has elapsed, the battery is connected to an internal 1M test resistor for one second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the battery warning output BW is asserted. Once asserted, BW remains active until the module is replaced. The battery is still retested after each V power-up, however, even if BW is active. If the battery voltage CC is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing resumes. BW has an open drain output driver. 2 of 10