Data Sheet BCM5325E Integrated 10/100BASE-T/TX Six-Port Switch GENERAL DESCRIPTION FEATURES The BCM5325E is a six-port 10/100BASE-T/TX Six-port, 10/100 Mbps integrated switch controller fully non-blocking configuration integrated switch targeted at cost-sensitive Fast Ethernet Five integrated 10/100BASE-T/TX/EFX IEEE 802.3u managed switch systems. The device contains five full- compliant transceivers. duplex 10BASE-T/100BASE-TX Fast Ethernet Integrated full-duplex capable IEEE 802.3x-compliant transceivers, each of which performs all of the physical MACs layer interface functions for 10BASE-T Ethernet on CAT 64 KB on-chip packet buffer 3, 4, or 5 unshielded twisted-pair (UTP) cable and Media Independent Interface (MII) provided for an 100BASE-TX Fast Ethernet on CAT 5 UTP cable. additional TX/FX uplink to PHY or MAC. 100BASE-EFX is supported through the use of external Integrated address managementsupports up to 1K fiber optic transceivers. unicast addresses Port mirroring and Layer-3 IGMP snooping The BCM5325E device provides a very highly integrated IEEE 802.1p QoS packet classification with four solution. It combines all of the functions of a high-speed priority queues and DiffServ DSCP priorities in IPv4 and IPv6 switch system, including packet buffer, transceivers, 16 entries IEEE 802.1q-based and Port-based VLAN media access controllers (MACs), address management Supports IEEE 802.1x EAPOL higher layer protocol and a non-blocking switch controller, into a single EEPROM (93C46) allows further un-managed monolithic 0.18-m CMOS device. It complies with the capabilities IEEE 802.3, 802.3u, and 802.3x specifications, including 25-MHz crystal or oscillator the MAC control Pause frame and auto-negotiation Low-power 3.3/1.8V, 0.18 m CMOS technology subsections, providing compatibility with all industry- HP auto-MDIX function hardware selectable standard Ethernet and Fast Ethernet devices. This 128-pin MQFP package. function requires only a small low-cost microcontroller to Ingress/egress rate control initialize and configure the device. Pin compatible with BCM5325 Protected port capability DTE/DPM power over Ethernet detection LEDCLK LEDDATA LEDA (1:5) Bias LED Controller RDAC LEDB (1:5) LEDC (1:5) 10BASE-T/ RD+/- 1:5 MAC0-4 100BASE-TX XTALO TD+/- 1:5 Transceiver Global XTALI / CK25 Functions RESET TXD 3:0 TXEN TXER TXC RXD(3:0) 64 KB RXDV Packet Buffer CRS MAC5/ VLAN RXER MII Controller QoS COL Address RXC Management MDC MDIO LINK MII FDX MIB Counters MII SPD100 SCK QoS EN Switch SS / CS Logic SPI/EEPROM QoS FC DIS w/QoS MOSI / DI QoS PORT SEL 1:0 MISO / DO Figure 1: Functional Block Diagram 5325E-DS14-R 5300 California Avenue Irvine, California 92617 Phone: 949-926-5000 Fax: 949-926-5203 09/16/08BCM5325E Data Sheet 09/16/08 REVISION HISTORY Revision Date Description 5325E-DS14-R 09/16/08 Updated: FEATURES Rate Control Register on page 147. 5325E-DS13-R 04/22/08 Removed Figure 33, VDDBIAS Circuitry, on page 82. 5325E-DS12-R 06/01/07 Added: 100BASE-Enhanced FX on page 23 Vidiff (for full threshold and half threshold) and Vicm to Table 171, Recommended Operating Conditions, on page 177. TDV cm and VO symbols to Table 172, Electrical Characteristics, on page 178. 5325E-DS11-R 03/06/07 Updated: Figure 9, Normal MII Configuration, on page 48. Figure 10, Reversed MII Configuration, on page 49. Table 172, Electrical Characteristics, on page 177. Table 173, 128-MQFP Thermal CharacteristicsWithout Heat Sink (2-Layer PCB), on page 178 Added: Table 174, 128-MQFP Thermal CharacteristicsWithout Heat Sink (4-Layer PCB), on page 178. Table 175, 128-MQFP Thermal CharacteristicsWith Heat Sink, on page 178. 5325E-DS10-R 12/22/06 Updated: Table 29, Pseudo PHY MII Register Definitions, on page 63. 5325E-DS09-R 11/02/06 Updated: Table 41 on page 88. Added: LED Flash Control Register on page 95. LEDa Control Register on page 95. LEDb Control Register on page 96. LEDc Control Register on page 96. 5325E-DS08-R 07/18/06 Updated: TXD 0 should be pulled down during power-up (MII1 TXD 0 on page 81). TXD 1 should be pulled down during power-up (MII1 TXD 1 on page 81). DNC list of signal description includes pin 43 (DNC on page 83). Ingress Mirror Divider Register on page 106. Egress Mirror Divider Register on page 108. 5325E-DS07-R 04/19/06 Updated: MIB Engine on page 45. Table 142, IEEE 802.1Q VLAN Registers (Page 0x34), on page 154. Table 143, IEEE 802.1Q VLAN Control 0 Register (Page: 0x34, Address 0x00), on page 155. Table 152, Default IEEE 802.1Q Tag Register Address Summary, on page 162. Table 166, Reverse MII Mode Output Timings, on page 173. Table 172, Electrical Characteristics, on page 178. Broadcom Corporation Page ii Document 5325E-DS14-R