Product Brief BCM5340X/BCM5341X 160 Gb/s Multilayer Switch Overview Features The Broadcom BCM5340X/ Highly integrated 16-port 10 BCM5341X System-on-a-Chip Gb/s Ethernet switch SoC with (SoC) switch family offers integrated 10G SerDes and industry-leading integration and optional CPU. performance in a small footprint. Diverse selection of natively The device offers up to 16 supported interfaces (KX, multilayer 10GbE ports. Offering KR, XFI, XAUI, RXAUI, SGMII, the industrys highest level of QSGMII). integration, the BCM5340X/ Key Features Support for port extender BCM5341X family of switches has Low-power 10GbE switch. applications (HiGig) with embedded SerDes supporting Small footprint, low-power, Priority-based Flow Control KX, KR, XFI, XAUI, RXAUI, SGMII, and flexible switch based on (PFC). and QSGMII modes, as well as an StrataConnect architecture. optional powerful Arm A9 single- Timestamping support with Diverse I/O and speed support core processor. The BCM5340X/ IEEE1588 transparent clock (TC) for embedded control/data BCM5341X is ideal for cost- and Synchronized Ethernet plane, backplane, and WebSmart sensitive connectivity applications, (SyncE), as well as OAM (IEEE applications. such as embedded designs for 802.1ag). control/data plane applications, or L2+ features include ACL, eight Nonblocking architecture line WebSmart switches for Small and Class of Service queues, and VLAN rate for all packet sizes. Medium Businesses (SMBs). translation. Fully integrated packet buffer. Optional integrated Arm A9 CPU. The BCM5340X/BCM5341X Intelligent Memory Management Integrated 10G SerDes with diverse device family offers multiple Unit (MMU) optimized for I/O for multiple configurations. I/O configurations and speeds handling bursty data traffic. (1G/2.5G/5G/10G) that address key Advanced single-stage L2, IPv4/IPv6 L3 packet segments of connectivity. ContentAware Engine for ACL and classification. DoS. With an integrated packet buffer Flexible Access Control List Optimized for Embedded control/ and the industrys lowest power (ACL). data plane and WebSmart consumption, the BCM5340X/ applications in SMB networks. IPv4 and IPv6 L3 routing BCM5341X family of switches is support. designed to reduce overall system Nonblocked, full wirespeed performance for 16x 10GbE systems. costs. Enhanced DoS attack statistics gathering. OAM support with IEEE 802.1ag. The optimized I/O map reduces Timestamping support with 1588 TC EEE support. system design effort and enables and SyncE. low-cost PCB design. The Support for industrial BCM5340X/BCM5341X device Enhanced buffer management for temperatures. family offers many advanced robust burst absorption. Low power consumption. features, such as IEEE 802.1Q IPv4 and IPv6 support. VLAN, VLAN translation, enhanced Optional high performance Arm Low-power Energy Efficient Denial of Service (DoS) protection, A9 processor Ethernet support. IPv4 and IPv6 support, an Enables multiple SerDes advanced ContentAware Engine, configurations of 1G, 2.5G, 5G, and IEEE 802.1p Quality of Service and 10G. (QoS). StrataConnect Switching TechnologyProduct Brief Figure. BCM5340X/BCM5341X Block Diagram Benefits 4x 1G/2.5G 4x 1G/2.5G Based on industry-leading and or 1x XAUI or 4x QSGMII or 2x RXAUI or 1x XAUI market-proven StrataConnect USB PCIe DDR GMII architecture. Single-chip switch SoC optimized for embedded control/data plane as well as WebSmart connectivity PCIe DDR USB Core SerDes SerDes GbE MAC Core Controller applications for SMB networks. Flexible I/O configuration support ContentAware Processor for future-proofing. Classify, Filter, Modify, Redirect ARM A9 Seamless connection to StrataXGS fabric using IFP the HiGig2 or HiGig+ D-Cache I-Cache (recommended) protocol. Enhanced buffer management delivers optimum usage of L3 Processing L2 Cache packet-buffer resources. L2 Processing Eight flexible Class of Service queues per port assure the lowest latency to high-priority ARM R5 traffic. Packet Buffer IPv6 support provides future- Meters, Counters D-Cache I-Cache proofing. Leverages the Broadcom unified API for software reuse and quick SerDes SerDes SerDes SerDes time-to-market. Optimized ball pattern for low- cost PCB design. 4x 1G/2.5G/10G 4x 1G/2.5G/10G 4x 1G/2.5G/10G 4x 1G/2.5G/10G or 1x XAUI or 1x XAUI or 1x XAUI or 1x XAUI or 2x RXAUI or 2x RXAUI or 2x RXAUI or 2x RXAUI 16x 1G/2.5G/5G/10G Ordering Information Part Number Description BCM53412 8x 1G/2.5G/5G/10G (integrated CPU) BCM53402 8x 1G/2.5G/5G/10G (no CPU) BCM53416 12x 1G/2.5G/5G/10G + 12x 1G/2.5G (integrated CPU) BCM53406 12x 1G/2.5G/5G/10G + 12x 1G/2.5G (no CPU) BCM53415 16x 1G/2.5G/5G/10G (integrated CPU) BCM53405 16x 1G/2.5G/5G/10G (no CPU) For more product information: broadcom.com Copyright 2020 Broadcom. All Rights Reserved. Broadcom, the pulse logo, ContentAware, HiGig, HiGig+, HiGig2, StrataConnect, StrataXGS, and Connecting everything are among the trademarks of Broadcom. The term Broadcom refers to Broadcom Inc. and/or its subsidiaries. 5340X-PB102 June 11, 2020