Data Sheet BCM5396 Single-Chip 16-Port SerDes Gigabit Switch The BCM5396 is a 16-port Gigabit Ethernet (GbE) 16-port 10/100/1000 Mbps integrated switch controller via 1.25G SerDes/SGMII/fiber switch integrated with 16 1.25G SerDes/SGMII port interfaces for connecting to external Gigabit PHYs or Embedded 256 KB on-chip packet buffer fiber modules. The BCM5396 provides the lowest- One 10/100/1000 Mbps In-band Management Port power and cost GbE functionality to the desktop (IMP) with GMII/RGMII/RvMII/MII interface for switching solution or WebSmart application. PHY-less connection to a CPU/management entity (for management purposes only) The BCM5396 is a highly integrated solution, Integrated address management combining all of the functions of a high-speed switch Supports up to 4K MAC addresses system, including packet buffer, Media Access Supports jumbo frames up to 9728 bytes. Controllers (MACs), address management, and a non-blocking switch controller into a single monolithic Supports EEPROM for low-cost chip configuration 0.13 m CMOS device. The BCM5396 complies with Integrated Motorola SPI-compatible interface the IEEE 802.3, 802.3u, 802.3ab, and 802.3x Supports port mirroring specifications, including the MAC control PAUSE Port-based VLAN and 4K IEEE 802.1Q tag VLAN frame and auto-negotiation subsections, providing Port-, DiffServ-, MAC-, and IEEE 802.1p-based compatibility with all industry-standard Ethernet, Fast QoS for four queues Ethernet, and GbE devices. Supports Spanning Tree, Rapid Spanning Tree, The BCM5396 device provides integrated 1.25G and Multiple Spanning Tree protocols (802.1D/1s/1w) SerDes, reducing board footprint requirements. The 16 ports have SGMII interfaces for connecting with Supports IEEE Standard 802.1X port security external GbE transceivers. Supports pseudo-PHY MDIO access MAC-based trunking with link fail-over Ethernet-in-the-last-mile (EFM) support: OAM and P Low-power (2.2W total) 1.2V core/2.5V (SGMII I/O)/3.3V (GMII/MII/RvMII) and 2.5V RGMII operation with 3.3V I/O tolerance 256-pin FBGA package 5396-DS116-R Corporate Headquarters: San Jose, CA June 20, 2016Figure 1: Functional Block Diagram Internal SerDes Deserializer/ Regulators Interface Gigabit MAC Gigabit MAC Serializer Port 0 SerDes Deserializer/ Interface Gigabit MAC Gigabit MAC Serializer MDC/MDIO Port 1 Interface Register Gigabit MAC Configuration Space Pins Gigabit MAC SPI Interface or EEPROM Interface SerDes Gigabit MAC Deserializer/ Internal Interface Gigabit MAC Serializer Memory Port 15 Gigabit MAC Address GMII/RGMII/MII/RvMII Gigabit MAC Management Interface 2016 by Broadcom. All rights reserved. Broadcom , the pulse logo, Connecting everything , Avago Technologies, and the A logo are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries and/or the EU. The term Broadcom refers to Broadcom Limited and/or its subsidiaries. For more information, please visit www.broadcom.com. Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.