Advance Data Sheet BCM56450 102.5 Gbps Integrated Multilayer Ethernet Switch and Traffic Manager GENERAL DESCRIPTION FEATURES The Broadcom BCM56450 is purpose-built for next- Integrated 2.0 MB packet buffer generation Carrier Ethernet EAdvance Data Sheetdge and Support for up to 720 MB of external packet buffer Mobile Backhaul platforms. It combines a feature-rich using six DDR3 SDRAMs packet processing engine, integrated hierarchical traffic Integrated hierarchical traffic manager supporting: manager, deep external packet buffer, address Four-level hierarchical scheduler management, and a non-blocking switch fabric into a single Min/Max rate guarantees at each scheduling 40 nm CMOS device. The BCM56450 supports an level integrated packet buffer with an external packet buffer MEF-compliant hierarchical metering with expansion option, utilizing economical DDR3 SDRAM 8 Kbps granularity technology. The BCM56450 is capable of handling L2 Supports double-tagging for IEEE 802.1ad switching, L3 routing, metro VPN tunneling, and access provider bridging, Broadband Forum TR-101, and control lists (ACLs). The BCM56450 virtualized architecture TR-156 enables seamless support for VPLS, VPWS, MPLS-TP, Supports VLAN translation in both ingress and PBB, and PBB-TE tunneling. In addition, the BCM56450 egress supports internal processing of Ethernet OAM and BFD to Supports Multi-protocol Label Switching (MPLS) enable a complete host CPU offload for these functions. for L2 VPLS/VPWS and L3 MPLS services The BCM56450 has three ContentAware processors Supports IEEE 802.1ah provider backbone distributed throughout various stages of the pipeline to bridging and IEEE 802.1Qay provider backbone allow actions to be taken based on various matching bridging with traffic engineering criteria.The device complies with IEEE 802.3, IEEE 802.3u, Ethernet OAM support in hardware (IEEE 802.1ag IEEE 802.3ab, and IEEE 802.3x specifications. It and ITU Y.1731) incorporates 10 flex XAUI cores, each core provides up to Supports hardware-based IP multicast routing, 4x 1GbE, 4x 2.5GbE, or 1x 10GbE. Within the 10 flex XAUI forwarding, replication, and tunneling cores, there are up to four stacking ports that can be Advanced ContentAware processor for VLAN, configured as HiGig2 stacking ports. Multiple BCM56450 ingress, and egress devices can be connected together using the stacking links Advanced security features in hardware to create high port density systems. The BCM56450 Supports port trunking and mirroring across stack supports flexible Quality of Service (QoS), including IEEE Supports advanced packet flow control: Head of 802.1p and DiffServ/TOS. Up to 64K MAC addresses, 4K VLANs, STP, and IEEE 802.1x MAC security are Line (HOL) blocking prevention, back pressure supported. The device integrates a dual-core ARM Cortex Supports packet classification using IEEE 802.1p A9 processor running at 1 GHz to allow a complete solution QoS or DiffServ/TOS priority to be developed without an external host processor. The Low power 40 nm CMOS process device also provides a two-lane PCI Express interface that 48 QoS queues for CPU can be configured to operate as a Root Complex or End- RFC3176 sFlow traffic monitoring Point. Virtual Route and Forwarding (VRF) support The BCM56450 also offers unparalleled integration for Equal cost multipath (ECMP) and weighted cost supporting Ethernet time synchronization. Synchronous multipath (WCMP) Ethernet Clock recovery is supported on any of the ports to Integrated host processor with dual ARM cores support physical layer clock synchronization. In addition to Ethernet channelization support through the use of physical layer clock synchronization, the BCM56450 also an additional tag provides hooks for both 1588v2 and IEEE 802.1as packet- G.999.1 fragmentation and Ethernet Adaptation based clock synchronization and offers an integrated DPLL support for recovered clock cleanup, as well as G.823- and G.824- compliant clock synthesizer to reduce overall cost and ease production. 56450-DS107 Corporate Headquarters: San Jose, CA December 21, 2016 Broadcom Confidential for gabriel.cassaro broadcom.comFigure 1: Functional Block Diagram 2x SGMII Management 2x Flexible XAUI/HG 13 4x XFI/KR or HG 21 , HG 13 36-bit iProc Dual-Core WC WC F-XAUI F-XAUI DDR3 ARM A9 6x 16-bit DDR3 Memory G.999.1 LINK-PHY DDR3 Controller H-QoS Scheduler and Flexible Queues Integrated Buffer L2/L3MPLS Packet Processing FP Classifier Time Sync I/O and PLLs Service Meters OAM Engine Flexible Counters Ethernet Channelization 1588 Timestamping and Clock Recovery F- F- F- F- F- GS F-XAUI XAUI XAUI XAUI XAUI XAUI 6x Flexible XAUIs 1G/2.5G Broadcom, the pulse logo, Connecting everything, Avago, Avago Technologies, and the A logo are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries and/or the EU. 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