VERSION 1.0 2002
PCI 9056
Connectivity
32-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola
32-bit, 66MHz PCI r2.2 compliant
PowerQUICC and Generic 32-bit, 66MHz Local Bus Designs
Motorola PowerQUICC and
generic 32-bit, 66MHz local bus
modes
Highest Performance 32-bit PCI Bus Mastering I/O Accelerator
3.3V I/O, 5V tolerant bus
interfaces for Your Embedded Applications
PICMG 2.1 r2.0 Hot Swap Silicon The PCI 9056 offers flexible connectivity and high performance I/O acceleration features
to enable leading edge PCI, CompactPCI, and embedded host designs.
256-ball, 17 x 17 mm, 1.00 mm
fine pitch PBGA (FPBGA)
Motorola MPC 850/860 PowerQUICC Designs
The PCI 9056 is the perfect match for the industry leading 32-bit communications proces-
Performance
sor, the Motorola MPC 850/860 PowerQUICC. The PCI 9056 provides a direct connection
Zero wait state burst operation
to PowerQUICC devices, enabling high-speed 32-bit, 66MHz PCI performance utilizing
PCI bus bursts to 264 MB/sec
PLXs Data Pipe Architecture technology.
Local bus bursts to 264 MB/sec
Generic 32-bit, 66MHz Local Bus Designs
2 DMA Channels
The PCI 9056 provides direct connection to two generic industry standard interconnect
Block & Scatter/Gather transfers
buses. Designers use these 32-bit, 66MHz buses for a myriad of high-speed devices
DMA descriptor ring management
ranging from processors, to DSPs, to memories, to custom ASICs and FPGAs. The PCI
Demand Mode & EOT H/W 9056 Data Pipe Architecture technology enables high-speed, 32-bit, 66MHz PCI I/O
controls
with those devices.
Direct Master data transfers
Move Your 32-bit Embedded Designs Up to 66MHz Operation
Generate any PCI transaction
As PCI evolves to meet the ever increasing I/O demands of leading edge communications
Read ahead and programmable
systems, PLX continues to provide high performance PCI I/O acceleration solutions. Based
read prefetch counter
on the architecture of the industry-leading PCI 9054, the PCI 9056 offers a variety of
Direct Slave data transfers
enhancements for the needs of todays telecom, networking, and I/O adapter designs:
Access 8-, 16-, and 32-bit local
32-bit, 66MHz PCI operation
bus devices
32-bit, 66MHz local bus operation
Deferred reads, deferred writes,
Dynamic DMA descriptor ring management with Valid bit semaphore control
read ahead, posted writes, pro-
PICMG 2.1 r2.0 Hot Swap Silicon, including Bias Voltage, Early Power,
grammable read prefetch counter
and Initialy Not Responding Support
Control
PCI Power Management r1.1 D3 Power Management Event (PME) generation
COLD
I O r1.5 messaging unit
2
PCI arbiter supporting 7 external masters
Eight mailbox and two
Reset and interrupt pins configurable for embedded host applications
doorbell registers
JTAG boundary scan
PCI arbiter supports 7 external
masters
The PCI 9056 is register compatible with the PCI 9054, enabling easy software migration.
Host mode reset/interrupt signal
configuration
PCI D3 Power Management
COLD
Event (PME) generation support
Serial EEPROM interface
JTAG boundary scan
PCI 9056 Features Serial EEPROM Independent 32 Lword (128 byte) read and
Stores configuration register power on, 64 Lword (256 byte) write FIFOs
The PCI 9056 32-bit, 66MHz PCI I/O accelera-
reset values
Deferred reads, deferred writes, posted
tor is the most advanced, 32-bit general-pur-
An alternative to expansion ROM for writes, read ahead, and programmable read
pose bus mastering device available for
storing Vital Product Data (VPD) prefetch counter
Motorola MPC 850/860 PowerQUICC and
Supports 2 Kbit/4 Kbit microwire devices Programmable READY# time out
generic 32-bit, 66MHz local bus based
with sequential read and recovery
designs. The PCI 9056 incorporates PLXs
Advanced Performance Features Common to
industry leading Data Pipe Architecture Data Pipe Architecture
DMA, Direct Master, and Direct Slave
technology, featuring DMA engines, program-
DMA
Zero wait state PCI and local bus bursts
mable Direct Master and Direct Slave data
Service DMA descriptors, mastering on both
Deep FIFOs prolong bursts
transfer modes, and PCI messaging functions.
bus interfaces during data transfer
Unaligned PCI and local bus transfers of
Two independent channels provide flexible
Interfaces
any byte length
prioritization scheme
PCI
On-the-fly Endian conversion
Each channel has its own bi-directional
32-bit, 66MHz r2.2 operation
64 Lword (256 byte) deep FIFO
Programmable local bus wait states
Zero wait state bursts to 264 MB/s
Block Mode services a single DMA Parity checking on both buses
Dual Address Cycle (DAC) support as a
descriptor in PCI 9056 registers
PCI bus master Messaging
Scatter/Gather Mode services DMA
Provides industry standard I O r1.5
2
Vital Product Data (VPD)
descriptor linked lists in memory
messaging unit
3.3V I/O, 5V tolerant
Burst descriptors from PCI or local
Supports general-purpose messaging for
PICMG 2.1 r2.0 Hot Swap Silicon bus memory
proprietary message schemes
Programming Interface 0 (PI=0)
Descriptor lists either linear (static)
Eight 32-bit mailbox registers for polled
or circular (dynamic) with Valid bit
environments
Bias Voltage Support
semaphore control
Two 32-bit doorbell registers for interrupt
Early Power Support
Direct Hardware DMA controls
driven environments
Intially Not Responding Support
Demand Mode to pause/resume
PCI Hot Plug r1.0 Embedded Host Features
End of Transfer (EOT) to abort
PCI arbiter supports 7 external masters
PCI Power Management r1.1
Programmable local bus burst length,
Reset and interrupt signals configurable for
Supports D0, D1, D2, D3 , and D3
HOT COLD including infinite
embedded host operation
power states
Enhanced M Mode supports bursts beyond
Type 0/1 Configuration support allows
D3 Power Management Event (PME)
COLD PowerQUICC 16 byte limit
local bus master to configure PCI bus
generation to meet PC 2001 Windows
and devices
Direct Master
98/2000 communication adapter logo
certification requirements Service local bus masters by mastering on
Package
the PCI bus
Local Bus
256-ball fine pitch PBGA (FPBGA)
Two local bus address spaces map to
Three local bus options on the device
17 mm x 17 mm, 1.00 mm ball pitch
PCI bus: one to memory; one to I/O
M Mode: Motorola MPC 850/860
Low power 2.5V CMOS core
Generate all PCI memory and I/O transac-
PowerQUICC and PowerPC 80x/82x
tion types, including Memory Write and 3.3V I/O, 5V tolerant
C Mode: De-multiplexed address and data
Invalidate (MWI)
Industrial temperature range operation
buses for Intel i960(r), DSPs, custom ASICs
Independent 32 Lword (128 byte) read
and FPGAs, and others
IEEE 1149.1 JTAG boundary scan
and 64 Lword (256 byte) write FIFOs
J Mode: Multiplexed address and data buses
Backward Compatibility
Read ahead and programmable read
for Intel i960, IBM PowerPC 401, IDT
prefetch counter The PCI 9056 register set is backward
RC32364, DSPs, PLX IOP 480, and others
compatible with the PCI 9054, with
32-bit, 66MHz operation PowerQUICC deferred reads and IDMA
new registers added for functionality
(M mode only)
Zero wait state bursts to 264 MB/s
enhancements
Direct Slave
3.3V I/O, 5V tolerant
Related PLX Products
Service PCI bus masters by mastering on
Asynchronous clock inputs to PCI and
Support for 64-bit, 66MHz PCI with 32-bit,
the local bus
local bus
66MHz C, J, and M Local Bus Support is
Two general-purpose and one expansion
provided by the PCI 9656
ROM PCI address spaces map to local
See the PCI 9656 product brief for details
bus memory
Each address space may specify 8-, 16-, or
32-bit local bus data transfers